#include "../../../southbridge/amd/cs5536/cs5536.h"
#define VIDEO_MB 8
-extern void graphics_init(void);
-
#define NORTHBRIDGE_FILE "northbridge.c"
-/* todo: add a resource record. We don't do this here because this may be called when
+/* todo: add a resource record. We don't do this here because this may be called when
* very little of the platform is actually working.
*/
int
};
/* note that dev is NOT used -- yet */
-static void irq_init_steering(struct device *dev, uint16_t irq_map) {
+static void irq_init_steering(struct device *dev, u16 irq_map) {
/* Set up IRQ steering */
- uint32_t pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
+ u32 pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
- printk(BIOS_DEBUG, "%s(%08X [%08X], %04X)\n", __func__, dev, pciAddr, irq_map);
+ printk(BIOS_DEBUG, "%s(%p [%08X], %04X)\n", __func__, dev, pciAddr, irq_map);
/* The IRQ steering values (in hex) are effectively dcba, where:
- * <a> represents the IRQ for INTA,
+ * <a> represents the IRQ for INTA,
* <b> represents the IRQ for INTB,
* <c> represents the IRQ for INTC, and
* <d> represents the IRQ for INTD.
/*
* setup_gx2_cache
*
- * Returns the amount of memory (in KB) available to the system. This is the
+ * Returns the amount of memory (in KB) available to the system. This is the
* total amount of memory less the amount of memory reserved for SMM use.
*
- */
+ */
static int
setup_gx2_cache(void)
{
}
/* we have to do this here. We have not found a nicer way to do it */
-void
+static void
setup_gx2(void)
{
membytes = size_kb * 1024;
/* NOTE! setup_gx2_cache returns the SIZE OF RAM - RAMADJUST!
- * so it is safe to use. You should NOT at this point call
- * sizeram() directly.
+ * so it is safe to use. You should NOT at this point call
+ * sizeram() directly.
*/
/* we need to set 0x10000028 and 0x40000029 */
/*
- * These two descriptors cover the range from 1 MB (0x100000) to
+ * These two descriptors cover the range from 1 MB (0x100000) to
* SYSTOP (a.k.a. TOM, or Top of Memory)
*/
/* calculate the PBASE and PMASK fields */
tmp2 = (SMM_OFFSET << 8) & 0xFFF00000; /* shift right 12 then left 20 == left 8 */
tmp2 |= (((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff);
- printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2);
+ printk(BIOS_DEBUG, "MSR 0x%x is now 0x%lx:0x%lx\n", 0x10000026, tmp, tmp2);
msr.hi = tmp;
msr.lo = tmp2;
wrmsr(0x10000026, msr);
static void enable_shadow(device_t dev)
{
-
+
}
-static void northbridge_init(device_t dev)
+static void northbridge_init(device_t dev)
{
unsigned long m;
struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info;
printk(BIOS_DEBUG, "northbridge: %s()\n", __func__);
-
+
enable_shadow(dev);
irq_init_steering(dev, nb->irqmap);
/* this is a test -- we are not sure it will work -- but it ought to */
static void set_resources(struct device *dev)
{
- struct resource *resource, *last;
- unsigned link;
- uint8_t line;
-
#if 0
- last = &dev->resource[dev->resources];
+ struct resource *res;
- for(resource = &dev->resource[0]; resource < last; resource++) {
+ for(res = &dev->resource_list; res; res = res->next) {
pci_set_resource(dev, resource);
}
#endif
- for(link = 0; link < dev->links; link++) {
- struct bus *bus;
- bus = &dev->link[link];
+ struct bus *bus;
+
+ for(bus = dev->link_list; bus; bus = bus->next) {
if (bus->children) {
assign_resources(bus);
}
}
/* zero the irq settings */
- line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
+ u8 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
if (line) {
pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
}
.device = PCI_DEVICE_ID_NS_GX2,
};
-static void ram_resource(device_t dev, unsigned long index,
- unsigned long basek, unsigned long sizek)
-{
- struct resource *resource;
-
- if (!sizek) {
- return;
- }
- resource = new_resource(dev, index);
- resource->base = ((resource_t)basek) << 10;
- resource->size = ((resource_t)sizek) << 10;
- resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-}
-
-static void tolm_test(void *gp, struct device *dev, struct resource *new)
-{
- struct resource **best_p = gp;
- struct resource *best;
- best = *best_p;
- if (!best || (best->base > new->base)) {
- best = new;
- }
- *best_p = best;
-}
-
-#if 0
-static uint32_t find_pci_tolm(struct bus *bus)
-{
- struct resource *min;
- uint32_t tolm;
- min = 0;
- search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
- tolm = 0xffffffffUL;
- if (min && tolm > min->base) {
- tolm = min->base;
- }
- return tolm;
-}
-#endif
+// FIXME handle UMA correctly.
#define FRAMEBUFFERK 4096
static void pci_domain_set_resources(device_t dev)
{
#if 0
device_t mc_dev;
- uint32_t pci_tolm;
+ u32 pci_tolm;
- pci_tolm = find_pci_tolm(&dev->link[0]);
- mc_dev = dev->link[0].children;
+ pci_tolm = find_pci_tolm(dev->link_list);
+ mc_dev = dev->link_list->children;
if (mc_dev) {
unsigned int tomk, tolmk;
unsigned int ramreg = 0;
continue;
ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2);
}
-
+
tomk = ramreg << 10;
/* Sort out the framebuffer size */
ram_resource(dev, idx++, 0, tolmk);
}
#endif
- assign_resources(&dev->link[0]);
+ assign_resources(dev->link_list);
}
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
- .enable_resources = enable_childrens_resources,
- .init = 0,
+ .enable_resources = NULL,
+ .init = NULL,
.scan_bus = pci_domain_scan_bus,
-};
+};
static void cpu_bus_init(device_t dev)
{
- initialize_cpus(&dev->link[0]);
+ initialize_cpus(dev->link_list);
}
static void cpu_bus_noop(device_t dev)
static void enable_dev(struct device *dev)
{
printk(BIOS_DEBUG, "gx2 north: enable_dev\n");
- void northbridgeinit(void);
- void chipsetinit(struct northbridge_amd_gx2_config *nb);
void do_vsmbios(void);
+
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
- struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info;
- extern void cpubug(void);
u32 tomk;
printk(BIOS_DEBUG, "DEVICE_PATH_PCI_DOMAIN\n");
/* cpubug MUST be called before setup_gx2(), so we force the issue here */
northbridgeinit();
- cpubug();
- chipsetinit(nb);
+ cpubug();
+ chipsetinit();
setup_gx2();
do_vsmbios();
graphics_init();
struct chip_operations northbridge_amd_gx2_ops = {
CHIP_NAME("AMD GX (previously GX2) Northbridge")
- .enable_dev = enable_dev,
+ .enable_dev = enable_dev,
};
projects / coreboot.git / blobdiff