#include <cpu/x86/msr.h>
#include <cpu/x86/cache.h>
#include <cpu/amd/vr.h>
+#include <cpu/cpu.h>
#include "../../../southbridge/amd/cs5536/cs5536.h"
#define VIDEO_MB 8
unsigned short dimm;
msr = rdmsr(0x20000018);
- printk_debug("sizeram: %08x:%08x\n", msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "sizeram: %08x:%08x\n", msr.hi, msr.lo);
/* dimm 0 */
dimm = msr.hi;
if ((dimm & 7) != 7)
sizem += (1 << ((dimm >> 12)-1)) * 8;
- printk_debug("sizeram: sizem 0x%x\n", sizem);
+ printk(BIOS_DEBUG, "sizeram: sizem 0x%x\n", sizem);
return sizem;
}
/* Set up IRQ steering */
uint32_t pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
- printk_debug("%s(%08X [%08X], %04X)\n", __FUNCTION__, dev, pciAddr, irq_map);
+ printk(BIOS_DEBUG, "%s(%08X [%08X], %04X)\n", __func__, dev, pciAddr, irq_map);
/* The IRQ steering values (in hex) are effectively dcba, where:
* <a> represents the IRQ for INTA,
int sizekbytes, sizereg;
sizekbytes = sizeram() * 1024;
- printk_debug("setup_gx2_cache: enable for %d KB\n", sizekbytes);
+ printk(BIOS_DEBUG, "setup_gx2_cache: enable for %d KB\n", sizekbytes);
/* build up the rconf word. */
/* the SYSTOP bits 27:8 are actually the top bits from 31:12. Book fails to say that */
/* set romrp */
val |= RAM_PROPERTIES;
msr.lo = val;
msr.hi = (val >> 32);
- printk_debug("msr 0x%08X will be set to %08x:%08x\n", CPU_RCONF_DEFAULT, msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "msr 0x%08X will be set to %08x:%08x\n", CPU_RCONF_DEFAULT, msr.hi, msr.lo);
wrmsr(CPU_RCONF_DEFAULT, msr);
enable_cache();
#if 0
/* This has already been done elsewhere */
- printk_debug("size_kb 0x%x, membytes 0x%x\n", size_kb, membytes);
+ printk(BIOS_DEBUG, "size_kb 0x%x, membytes 0x%x\n", size_kb, membytes);
msr.hi = 0x20000000 | membytes>>24;
msr.lo = 0x100 | ( ((membytes >>12) & 0xfff) << 20);
wrmsr(0x10000028, msr);
#endif
#if 0
msr = rdmsr(0x10000028);
- printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo);
+ printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x10000028, msr.hi,msr.lo);
msr = rdmsr(0x40000029);
- printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo);
+ printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x40000029, msr.hi,msr.lo);
#endif
#if 1
/* fixme: SMM MSR 0x10000026 and 0x400000023 */
/* calculate the PBASE and PMASK fields */
tmp2 = (SMM_OFFSET << 8) & 0xFFF00000; /* shift right 12 then left 20 == left 8 */
tmp2 |= (((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff);
- printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2);
+ printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, tmp, tmp2);
msr.hi = tmp;
msr.lo = tmp2;
wrmsr(0x10000026, msr);
msr.lo = 0x400fffc0;
wrmsr(0x10000026, msr);
msr = rdmsr(0x10000026);
- printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x10000026, msr.hi, msr.lo);
#endif
#if 0
msr.hi = 0x22fffc02;
msr.lo = 0x10ffbf00;
wrmsr(0x1808, msr);
msr = rdmsr(0x1808);
- printk_debug("MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo);
+ printk(BIOS_DEBUG, "MSR 0x%x is now 0x%x:0x%x\n", 0x1808, msr.hi, msr.lo);
#endif
#if 0 // SDG - don't do this
/* now do the default MSR values */
msr_t msr;
wrmsr(msr_defaults[i].msr_no, msr_defaults[i].msr); // MSR - see table above
msr = rdmsr(msr_defaults[i].msr_no);
- printk_debug("MSR 0x%08X is now 0x%08X:0x%08X\n", msr_defaults[i].msr_no, msr.hi,msr.lo);
+ printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", msr_defaults[i].msr_no, msr.hi,msr.lo);
}
#endif
}
unsigned long m;
struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info;
- printk_debug("northbridge: %s()\n", __FUNCTION__);
+ printk(BIOS_DEBUG, "northbridge: %s()\n", __func__);
enable_shadow(dev);
irq_init_steering(dev, nb->irqmap);
.ops_pci = 0,
};
-static struct pci_driver northbridge_driver __pci_driver = {
+static const struct pci_driver northbridge_driver __pci_driver = {
.ops = &northbridge_operations,
.vendor = PCI_VENDOR_ID_NS,
.device = PCI_DEVICE_ID_NS_GX2,
};
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
-
-static void pci_domain_read_resources(device_t dev)
-{
- struct resource *resource;
-
- printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __FUNCTION__);
-
- /* Initialize the system wide io space constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
- resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-
- /* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
- resource->limit = 0xffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
-}
-
static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek)
{
*bcdramtop = ((tomk << 10) - 1);
*mcgbaseadd = (tomk >> 9);
- printk_debug("BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
- printk_debug("MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
+ printk(BIOS_DEBUG, "BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
+ printk(BIOS_DEBUG, "MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
- printk_debug("I would set ram size to %d Mbytes\n", (tomk >> 10));
+ printk(BIOS_DEBUG, "I would set ram size to %d Mbytes\n", (tomk >> 10));
/* Compute the top of Low memory */
tolmk = pci_tolm >> 10;
assign_resources(&dev->link[0]);
}
-static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
-{
- max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
- return max;
-}
-
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
void chipsetInit (void);
+#if CONFIG_WRITE_HIGH_TABLES==1
+#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
+extern uint64_t high_tables_base, high_tables_size;
+#endif
+
static void enable_dev(struct device *dev)
{
- printk_debug("gx2 north: enable_dev\n");
+ printk(BIOS_DEBUG, "gx2 north: enable_dev\n");
void northbridgeinit(void);
void chipsetinit(struct northbridge_amd_gx2_config *nb);
- void setup_realmode_idt(void);
void do_vsmbios(void);
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info;
extern void cpubug(void);
- printk_debug("DEVICE_PATH_PCI_DOMAIN\n");
+ u32 tomk;
+ printk(BIOS_DEBUG, "DEVICE_PATH_PCI_DOMAIN\n");
/* cpubug MUST be called before setup_gx2(), so we force the issue here */
northbridgeinit();
cpubug();
chipsetinit(nb);
setup_gx2();
- /* do this here for now -- this chip really breaks our device model */
- setup_realmode_idt();
do_vsmbios();
graphics_init();
dev->ops = &pci_domain_ops;
pci_set_method(dev);
- ram_resource(dev, 0, 0, ((sizeram() - VIDEO_MB) * 1024) - SMM_SIZE);
+ tomk = ((sizeram() - VIDEO_MB) * 1024) - SMM_SIZE;
+#if CONFIG_WRITE_HIGH_TABLES==1
+ /* Leave some space for ACPI, PIRQ and MP tables */
+ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
+ high_tables_size = HIGH_TABLES_SIZE * 1024;
+#endif
+ ram_resource(dev, 0, 0, tomk);
} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
- printk_debug("DEVICE_PATH_APIC_CLUSTER\n");
+ printk(BIOS_DEBUG, "DEVICE_PATH_APIC_CLUSTER\n");
dev->ops = &cpu_bus_ops;
}
- printk_debug("gx2 north: end enable_dev\n");
+ printk(BIOS_DEBUG, "gx2 north: end enable_dev\n");
}
struct chip_operations northbridge_amd_gx2_ops = {
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