Add high tables support to all northbridges.

[coreboot.git] / src / northbridge / amd / gx1 / northbridge.c

diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c
index 247c24304e21691353fc40aba65d37fdad0bce48..63cc003df0a5eb36be78467e37c6337ea7a51f4f 100644 (file)
--- a/src/northbridge/amd/gx1/northbridge.c
+++ b/src/northbridge/amd/gx1/northbridge.c
@@ -126,6 +126,11 @@ static uint32_t find_pci_tolm(struct bus *bus)
        return tolm;
 }
 
+#if HAVE_HIGH_TABLES==1
+#define HIGH_TABLES_SIZE 64    // maximum size of high tables in KB
+extern uint64_t high_tables_base, high_tables_size;
+#endif
+
 static void pci_domain_set_resources(device_t dev)
 {
        device_t mc_dev;
@@ -168,6 +173,13 @@ static void pci_domain_set_resources(device_t dev)
                         */
                        tolmk = tomk;
                }
+
+#if HAVE_HIGH_TABLES==1
+               /* Leave some space for ACPI, PIRQ and MP tables */
+               high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024;
+               high_tables_size = HIGH_TABLES_SIZE * 1024;
+#endif
+
                /* Report the memory regions */
                idx = 10;
                ram_resource(dev, idx++, 0, tolmk);