Remove a few more warnings from fam10.

[coreboot.git] / src / northbridge / amd / amdmct / mct / mct_d.c

diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index 105ae662b889fbd89d1ee3a96f1d864a2f0bb716..ef7e2af92a1ff1a7402f5dbf8927b95020d54061 100644 (file)
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -177,7 +177,7 @@ static const u8 Table_Comp_Rise_Slew_15x[] = {7, 7, 3, 2, 0xFF};
 static const u8 Table_Comp_Fall_Slew_20x[] = {7, 5, 3, 2, 0xFF};
 static const u8 Table_Comp_Fall_Slew_15x[] = {7, 7, 5, 3, 0xFF};
 
-void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
+static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
                        struct DCTStatStruc *pDCTstatA)
 {
        /*
@@ -352,7 +352,7 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
        nv_DQSTrainCTL = 1;
 
        print_t("DQSTiming_D: mct_BeforeDQSTrain_D:\n");
-       mct_BeforeDQSTrain_D(pMCTstat, pDCTstatA);;
+       mct_BeforeDQSTrain_D(pMCTstat, pDCTstatA);
        phyAssistedMemFnceTraining(pMCTstat, pDCTstatA);
 
        if (nv_DQSTrainCTL) {
@@ -556,7 +556,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat,
                        base  += NextBase;
                        limit += NextBase;
                        DramSelBaseAddr += NextBase;
-                       printk_debug(" Node: %02x  base: %02x  limit: %02x  BottomIO: %02x\n", Node, base, limit, BottomIO);
+                       printk(BIOS_DEBUG, " Node: %02x  base: %02x  limit: %02x  BottomIO: %02x\n", Node, base, limit, BottomIO);
 
                        if (_MemHoleRemap) {
                                if ((base < BottomIO) && (limit >= BottomIO)) {
@@ -633,7 +633,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat,
                devx = pDCTstat->dev_map;
 
                if (pDCTstat->NodePresent) {
-               printk_debug(" Copy dram map from Node 0 to Node %02x \n", Node);
+               printk(BIOS_DEBUG, " Copy dram map from Node 0 to Node %02x \n", Node);
                        reg = 0x40;             /*Dram Base 0*/
                        do {
                                val = Get_NB32(dev, reg);
@@ -982,8 +982,8 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
                if ( mctGet_NVbits(NV_MCTUSRTMGMODE) == 2)
                        pDCTstat->Speed = mctGet_NVbits(NV_MemCkVal) + 1;
 
-               mct_AfterGetCLT(pMCTstat, pDCTstat, dct);
        }
+       mct_AfterGetCLT(pMCTstat, pDCTstat, dct);
 
        /* Gather all DIMM mini-max values for cycle timing data */
        Rows = 0;
@@ -1001,7 +1001,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
        for ( i = 0; i< MAX_DIMMS_SUPPORTED; i++) {
                LDIMM = i >> 1;
                if (pDCTstat->DIMMValid & (1 << i)) {
-                       smbaddr = Get_DIMMAddress_D(pDCTstat, i);
+                       smbaddr = Get_DIMMAddress_D(pDCTstat, dct + i);
                        byte = mctRead_SPD(smbaddr, SPD_ROWSZ);
                        if (Rows < byte)
                                Rows = byte;    /* keep track of largest row sz */
@@ -2472,22 +2472,13 @@ static u8 mct_setMode(struct MCTStatStruc *pMCTstat,
 
 u32 Get_NB32(u32 dev, u32 reg)
 {
-       u32 addr;
-
-       addr = (dev>>4) | (reg & 0xFF) | ((reg & 0xf00)<<16);
-       outl((1<<31) | (addr & ~3), 0xcf8);
-
-       return inl(0xcfc);
+       return pci_read_config32(dev, reg);
 }
 
 
 void Set_NB32(u32 dev, u32 reg, u32 val)
 {
-       u32 addr;
-
-       addr = (dev>>4) | (reg & 0xFF) | ((reg & 0xf00)<<16);
-       outl((1<<31) | (addr & ~3), 0xcf8);
-       outl(val, 0xcfc);
+       pci_write_config32(dev, reg, val);
 }
 
 
@@ -3574,7 +3565,7 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat,
        u8 Node;
        u32 i;
        struct DCTStatStruc *pDCTstat;
-       u16 start, stop;
+       u32 start, stop;
        u8 *p;
        u16 host_serv1, host_serv2;
 
@@ -3591,12 +3582,12 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat,
 
                p = (u8 *) pDCTstat;
                start = 0;
-               stop = ((u16) &((struct DCTStatStruc *)0)->CH_MaxRdLat[2]);
+               stop = (u32)(&((struct DCTStatStruc *)0)->CH_MaxRdLat[2]);
                for (i = start; i < stop ; i++) {
                        p[i] = 0;
                }
 
-               start = ((u16) &((struct DCTStatStruc *)0)->CH_D_BC_RCVRDLY[2][4]);
+               start = (u32)(&((struct DCTStatStruc *)0)->CH_D_BC_RCVRDLY[2][4]);
                stop = sizeof(struct DCTStatStruc);
                for (i = start; i < stop; i++) {
                        p[i] = 0;
@@ -3626,7 +3617,7 @@ static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat,
 }
 
 
-void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat,
+static void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat,
                        struct DCTStatStruc *pDCTstat, u8 *dqs_pos)
 {
        // FIXME: Skip for Ax