printk_foo -> printk(BIOS_FOO, ...)

[coreboot.git] / src / northbridge / amd / amdmct / mct / mct_d.c

diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index f29953a5c60097c36751fe2aa67d942f4c9789b9..ec767fa27c82c7c1498488687325443be87a5af8 100644 (file)
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -352,11 +352,11 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat,
        nv_DQSTrainCTL = 1;
 
        print_t("DQSTiming_D: mct_BeforeDQSTrain_D:\n");
-       mct_BeforeDQSTrain_D(pMCTstat, pDCTstatA);;
+       mct_BeforeDQSTrain_D(pMCTstat, pDCTstatA);
        phyAssistedMemFnceTraining(pMCTstat, pDCTstatA);
 
        if (nv_DQSTrainCTL) {
-               mctHookBeforeAnyTraining();
+               mctHookBeforeAnyTraining(pMCTstat, pDCTstatA);
 
                print_t("DQSTiming_D: TrainReceiverEn_D FirstPass:\n");
                TrainReceiverEn_D(pMCTstat, pDCTstatA, FirstPass);
@@ -556,7 +556,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat,
                        base  += NextBase;
                        limit += NextBase;
                        DramSelBaseAddr += NextBase;
-                       printk_debug(" Node: %02x  base: %02x  limit: %02x  BottomIO: %02x\n", Node, base, limit, BottomIO);
+                       printk(BIOS_DEBUG, " Node: %02x  base: %02x  limit: %02x  BottomIO: %02x\n", Node, base, limit, BottomIO);
 
                        if (_MemHoleRemap) {
                                if ((base < BottomIO) && (limit >= BottomIO)) {
@@ -633,7 +633,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat,
                devx = pDCTstat->dev_map;
 
                if (pDCTstat->NodePresent) {
-               printk_debug(" Copy dram map from Node 0 to Node %02x \n", Node);
+               printk(BIOS_DEBUG, " Copy dram map from Node 0 to Node %02x \n", Node);
                        reg = 0x40;             /*Dram Base 0*/
                        do {
                                val = Get_NB32(dev, reg);
@@ -982,8 +982,8 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
                if ( mctGet_NVbits(NV_MCTUSRTMGMODE) == 2)
                        pDCTstat->Speed = mctGet_NVbits(NV_MemCkVal) + 1;
 
-               mct_AfterGetCLT(pMCTstat, pDCTstat, dct);
        }
+       mct_AfterGetCLT(pMCTstat, pDCTstat, dct);
 
        /* Gather all DIMM mini-max values for cycle timing data */
        Rows = 0;
@@ -1001,7 +1001,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
        for ( i = 0; i< MAX_DIMMS_SUPPORTED; i++) {
                LDIMM = i >> 1;
                if (pDCTstat->DIMMValid & (1 << i)) {
-                       smbaddr = Get_DIMMAddress_D(pDCTstat, i);
+                       smbaddr = Get_DIMMAddress_D(pDCTstat, dct + i);
                        byte = mctRead_SPD(smbaddr, SPD_ROWSZ);
                        if (Rows < byte)
                                Rows = byte;    /* keep track of largest row sz */
@@ -2401,30 +2401,34 @@ static void mct_DramInit(struct MCTStatStruc *pMCTstat,
        mct_BeforeDramInit_Prod_D(pMCTstat, pDCTstat);
        // FIXME: for rev A: mct_BeforeDramInit_D(pDCTstat, dct);
 
-       /* Disable auto refresh before Dram init when in ganged mode */
-       if (pDCTstat->GangedMode) {
-               val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct));
-               val |= 1 << DisAutoRefresh;
-               Set_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct), val);
+       /* Disable auto refresh before Dram init when in ganged mode (Erratum 278) */
+       if (pDCTstat->LogicalCPUID & AMD_DR_LT_B2) {
+               if (pDCTstat->GangedMode) {
+                       val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct));
+                       val |= 1 << DisAutoRefresh;
+                       Set_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct), val);
+               }
        }
 
        mct_DramInit_Hw_D(pMCTstat, pDCTstat, dct);
 
        /* Re-enable auto refresh after Dram init when in ganged mode
-        * to ensure both DCTs are in sync
+        * to ensure both DCTs are in sync (Erratum 278)
         */
 
-       if (pDCTstat->GangedMode) {
-               do {
-                       val = Get_NB32(pDCTstat->dev_dct, 0x90 + (0x100 * dct));
-               } while (!(val & (1 << InitDram)));
+       if (pDCTstat->LogicalCPUID & AMD_DR_LT_B2) {
+               if (pDCTstat->GangedMode) {
+                       do {
+                               val = Get_NB32(pDCTstat->dev_dct, 0x90 + (0x100 * dct));
+                       } while (!(val & (1 << InitDram)));
 
-               WaitRoutine_D(50);
+                       WaitRoutine_D(50);
 
-               val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct));
-               val &= ~(1 << DisAutoRefresh);
-               val |= 1 << DisAutoRefresh;
-               val &= ~(1 << DisAutoRefresh);
+                       val = Get_NB32(pDCTstat->dev_dct, 0x8C + (0x100 * dct));
+                       val &= ~(1 << DisAutoRefresh);
+                       val |= 1 << DisAutoRefresh;
+                       val &= ~(1 << DisAutoRefresh);
+               }
        }
 }
 
@@ -2468,22 +2472,13 @@ static u8 mct_setMode(struct MCTStatStruc *pMCTstat,
 
 u32 Get_NB32(u32 dev, u32 reg)
 {
-       u32 addr;
-
-       addr = (dev>>4) | (reg & 0xFF) | ((reg & 0xf00)<<16);
-       outl((1<<31) | (addr & ~3), 0xcf8);
-
-       return inl(0xcfc);
+       return pci_read_config32(dev, reg);
 }
 
 
 void Set_NB32(u32 dev, u32 reg, u32 val)
 {
-       u32 addr;
-
-       addr = (dev>>4) | (reg & 0xFF) | ((reg & 0xf00)<<16);
-       outl((1<<31) | (addr & ~3), 0xcf8);
-       outl(val, 0xcfc);
+       pci_write_config32(dev, reg, val);
 }
 
 
@@ -3396,6 +3391,8 @@ static void SetODTTriState(struct MCTStatStruc *pMCTstat,
        u8 max_dimms;
 
        // FIXME: skip for Ax
+       
+       dev = pDCTstat->dev_dct;
 
        /* Tri-state unused ODTs when motherboard termination is available */
        max_dimms = (u8) mctGet_NVbits(NV_MAX_DIMMS);
@@ -3792,7 +3789,10 @@ static void mct_ResetDLL_D(struct MCTStatStruc *pMCTstat,
        u8 wrap32dis = 0;
        u8 valid = 0;
 
-       /* FIXME: Skip reset DLL for B3 */
+       /* Skip reset DLL for B3 */
+       if (pDCTstat->LogicalCPUID & AMD_DR_B3) {
+               return;
+       }
 
        addr = HWCR;
        _RDMSR(addr, &lo, &hi);
@@ -3885,8 +3885,7 @@ static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct) {
        u32 reg_off = 0x100 * dct;
        u32 dev = pDCTstat->dev_dct;
 
-       /* FIXME: Add B3 */
-       if (pDCTstat->LogicalCPUID & AMD_DR_B2) {
+       if (pDCTstat->LogicalCPUID & (AMD_DR_B2 | AMD_DR_B3)) {
                mct_Wait(10000);        /* Wait 50 us*/
                val = Get_NB32(dev, 0x110);
                if ( val & (1 << DramEnabled)) {