1. This patch adds CAR for Intel P6 series processors.

[coreboot.git] / src / northbridge / amd / amdk8 / raminit_f_dqs.c

diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index 4e402e6d7a3ac81ae91023a3ca78380b687037af..a668c9f1e02892bd80bb5bd547938c362a87e0d2 100644 (file)
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -18,6 +18,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */
 
+#include <arch/stages.h>
+
 //0: mean no debug info
 #define DQS_TRAIN_DEBUG 0
 
@@ -125,7 +127,7 @@ static inline void write_cr4(unsigned long cr4)
 }
 
 
-static inline void enable_sse2()
+static inline void enable_sse2(void)
 {
        unsigned long cr4;
        cr4 = read_cr4();
@@ -133,7 +135,7 @@ static inline void enable_sse2()
        write_cr4(cr4);
 }
 
-static inline void disable_sse2()
+static inline void disable_sse2(void)
 {
        unsigned long cr4;
        cr4 = read_cr4();
@@ -1824,12 +1826,12 @@ static void set_sysinfo_in_ram(unsigned val)
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 #else
-int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
+static int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
 {
        return nvram_pos;
 }
 
-int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
+static int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
 {
        die("No memory NVRAM loader for DQS data! Unable to restore memory state\n");
 
@@ -1837,12 +1839,14 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
 }
 #endif
 
+#if CONFIG_MEM_TRAIN_SEQ == 0
 static int save_index_to_pos(unsigned int dev, int size, int index, int nvram_pos)
 {
        u32 dword = pci_read_config32_index_wait(dev, 0x98, index);
 
        return s3_save_nvram_early(dword, size, nvram_pos);
 }
+#endif
 
 static int load_index_to_pos(unsigned int dev, int size, int index, int nvram_pos)
 {
@@ -1872,6 +1876,7 @@ static int dqs_load_MC_NVRAM_ch(unsigned int dev, int ch, int pos)
        return pos;
 }
 
+#if CONFIG_MEM_TRAIN_SEQ == 0
 static int dqs_save_MC_NVRAM_ch(unsigned int dev, int ch, int pos)
 {
        /* 30 bytes per channel */
@@ -1902,6 +1907,7 @@ static void dqs_save_MC_NVRAM(unsigned int dev)
        reg = pci_read_config32(dev, DRAM_CONFIG_HIGH);
        pos = s3_save_nvram_early(reg, 4, pos);
 }
+#endif
 
 static void dqs_restore_MC_NVRAM(unsigned int dev)
 {
@@ -2087,7 +2093,7 @@ static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info
        sysinfox->mem_trained[nodeid] = sysinfo->mem_trained[nodeid];
 
 }
-static void copy_and_run_ap_code_in_car(unsigned ret_addr);
+
 static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall)
 {
        if(coreid) return; // only do it on core0