Invalidate cache before first jump

[coreboot.git] / src / northbridge / amd / amdk8 / raminit_f_dqs.c

diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index 55cdcaf703bd92b4e19a3736fc57ccbc771aa211..8ddd44fadba68f454a900ec962c5541b1e983490 100644 (file)
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -18,6 +18,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 */
 
+#include <arch/stages.h>
+
 //0: mean no debug info
 #define DQS_TRAIN_DEBUG 0
 
@@ -25,7 +27,7 @@ static inline void print_debug_dqs(const char *str, unsigned val, unsigned level
 {
 #if DQS_TRAIN_DEBUG > 0
        if(DQS_TRAIN_DEBUG > level) {
-               printk(BIOS_DEBUG, "%s%x\r\n", str, val);
+               printk(BIOS_DEBUG, "%s%x\n", str, val);
        }
 #endif
 }
@@ -34,7 +36,7 @@ static inline void print_debug_dqs_pair(const char *str, unsigned val, const cha
 {
 #if DQS_TRAIN_DEBUG > 0
        if(DQS_TRAIN_DEBUG > level) {
-               printk(BIOS_DEBUG, "%s%08x%s%08x\r\n", str, val, str2, val2);
+               printk(BIOS_DEBUG, "%s%08x%s%08x\n", str, val, str2, val2);
        }
 #endif
 }
@@ -43,14 +45,14 @@ static inline void print_debug_dqs_tsc(const char *str, unsigned i, unsigned val
 {
 #if DQS_TRAIN_DEBUG > 0
        if(DQS_TRAIN_DEBUG > level) {
-               printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\r\n", str, i, val, val2);
+               printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\n", str, i, val, val2);
        }
 #endif
 }
 
 static inline void print_debug_dqs_tsc_x(const char *str, unsigned i, unsigned val, unsigned val2)
 {
-       printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\r\n", str, i, val, val2);
+       printk(BIOS_DEBUG, "%s[%02x]=%08x%08x\n", str, i, val, val2);
 
 }
 
@@ -125,7 +127,7 @@ static inline void write_cr4(unsigned long cr4)
 }
 
 
-static inline void enable_sse2()
+static inline void enable_sse2(void)
 {
        unsigned long cr4;
        cr4 = read_cr4();
@@ -133,7 +135,7 @@ static inline void enable_sse2()
        write_cr4(cr4);
 }
 
-static inline void disable_sse2()
+static inline void disable_sse2(void)
 {
        unsigned long cr4;
        cr4 = read_cr4();
@@ -434,7 +436,7 @@ static uint16_t get_exact_T1000(unsigned i)
                unsigned fid_start;
                msr = rdmsr(0xc0010015);
                fid_start = (msr.lo & (0x3f << 24));
-               
+
                index = fid_start>>25;
        }
 
@@ -526,7 +528,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st
        unsigned is_Width128 = sysinfo->meminfo[ctrl->node_id].is_Width128;
 
 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
-       unsigned cpu_f0_f1;
+       unsigned cpu_f0_f1 = 0;
 #endif
 
        if(Pass == DQS_FIRST_PASS) {
@@ -583,7 +585,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st
                }
        }
 
-       print_debug_dqs("\r\nTrainRcvEn: 0 ctrl", ctrl->node_id, 0);
+       print_debug_dqs("\nTrainRcvEn: 0 ctrl", ctrl->node_id, 0);
 
        print_debug_addr("TrainRcvEn: buf_a:", buf_a);
 
@@ -598,12 +600,12 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st
        }
 
        for ( ; (channel < 2) && (!Errors); channel++)
-       { 
-               print_debug_dqs("\tTrainRcvEn51: channel ",channel, 1); 
-               
-               /* for each rank */ 
-               /* there are four recriver pairs, loosely associated with CS */ 
-               for( receiver = 0; (receiver < 8) && (!Errors); receiver+=2) 
+       {
+               print_debug_dqs("\tTrainRcvEn51: channel ",channel, 1);
+
+               /* for each rank */
+               /* there are four recriver pairs, loosely associated with CS */
+               for( receiver = 0; (receiver < 8) && (!Errors); receiver+=2)
                {
 
                        unsigned index=(receiver>>1) * 3 + 0x10;
@@ -1401,7 +1403,7 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in
 
        }
 
-       print_debug_dqs("\r\nTrainDQSRdWrPos: 0 ctrl ", ctrl->node_id, 0);
+       print_debug_dqs("\nTrainDQSRdWrPos: 0 ctrl ", ctrl->node_id, 0);
 
        printk(BIOS_DEBUG, "TrainDQSRdWrPos: buf_a:%p\n", buf_a);
 
@@ -1525,25 +1527,25 @@ static void SetEccDQSRdWrPos(const struct mem_controller *ctrl, struct sys_info
 
 static unsigned train_DqsRcvrEn(const struct mem_controller *ctrl, unsigned Pass, struct sys_info *sysinfo)
 {
-       print_debug_dqs("\r\ntrain_DqsRcvrEn: begin ctrl ", ctrl->node_id, 0);
+       print_debug_dqs("\ntrain_DqsRcvrEn: begin ctrl ", ctrl->node_id, 0);
        if(TrainRcvrEn(ctrl, Pass, sysinfo)) {
                return 1;
        }
-       print_debug_dqs("\r\ntrain_DqsRcvrEn: end ctrl ", ctrl->node_id, 0);
+       print_debug_dqs("\ntrain_DqsRcvrEn: end ctrl ", ctrl->node_id, 0);
        return 0;
 
 }
 static unsigned train_DqsPos(const struct mem_controller *ctrl, struct sys_info *sysinfo)
 {
-       print_debug_dqs("\r\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0);
+       print_debug_dqs("\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0);
        if(TrainDQSRdWrPos(ctrl, sysinfo) != 0) {
-               printk(BIOS_ERR, "\r\nDQS Training Rd Wr failed ctrl%02x\r\n", ctrl->node_id);
+               printk(BIOS_ERR, "\nDQS Training Rd Wr failed ctrl%02x\n", ctrl->node_id);
                return 1;
        }
        else {
                SetEccDQSRdWrPos(ctrl, sysinfo);
        }
-       print_debug_dqs("\r\ntrain_DqsPos: end ctrl ", ctrl->node_id, 0);
+       print_debug_dqs("\ntrain_DqsPos: end ctrl ", ctrl->node_id, 0);
        return 0;
 
 }
@@ -1700,7 +1702,7 @@ static unsigned int range_to_mtrr(unsigned int reg,
                }
                sizek = 1 << align;
 #if CONFIG_MEM_TRAIN_SEQ != 1
-               printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\r\n",
+               printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n",
                        reg, range_startk >>10, sizek >> 10,
                        (type==MTRR_TYPE_UNCACHEABLE)?"UC":
                            ((type==MTRR_TYPE_WRBACK)?"WB":"Other")
@@ -1715,6 +1717,7 @@ static unsigned int range_to_mtrr(unsigned int reg,
        return reg;
 }
 
+#if CONFIG_MEM_TRAIN_SEQ == 1
 static void set_top_mem_ap(unsigned tom_k, unsigned tom2_k)
 {
        msr_t msr;
@@ -1728,6 +1731,7 @@ static void set_top_mem_ap(unsigned tom_k, unsigned tom2_k)
        msr.hi = (tom_k & 0xffc00000) >> 22;
        wrmsr(TOP_MEM, msr);
 }
+#endif
 
 static void setup_mtrr_dqs(unsigned tom_k, unsigned tom2_k)
 {
@@ -1800,6 +1804,7 @@ static void set_htic_bit(unsigned i, unsigned val, unsigned bit)
 }
 
 
+#if CONFIG_MEM_TRAIN_SEQ == 1
 static unsigned get_htic_bit(unsigned i, unsigned bit)
 {
        uint32_t dword;
@@ -1814,35 +1819,23 @@ static void wait_till_sysinfo_in_ram(void)
                if(get_htic_bit(0, 9)) return;
        }
 }
+#endif
 
 static void set_sysinfo_in_ram(unsigned val)
 {
        set_htic_bit(0, val, 9);
 }
 
-#ifdef S3_NVRAM_EARLY
-int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
-int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
-#else
-int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
-{
-       return nvram_pos;
-}
-
-int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
-{
-       die("No memory NVRAM loader for DQS data! Unable to restore memory state\n");
-
-       return nvram_pos; /* Make GCC happy */
-}
-#endif
+#if CONFIG_HAVE_ACPI_RESUME == 1
 
+#if CONFIG_MEM_TRAIN_SEQ == 0
 static int save_index_to_pos(unsigned int dev, int size, int index, int nvram_pos)
 {
        u32 dword = pci_read_config32_index_wait(dev, 0x98, index);
 
        return s3_save_nvram_early(dword, size, nvram_pos);
 }
+#endif
 
 static int load_index_to_pos(unsigned int dev, int size, int index, int nvram_pos)
 {
@@ -1872,6 +1865,7 @@ static int dqs_load_MC_NVRAM_ch(unsigned int dev, int ch, int pos)
        return pos;
 }
 
+#if CONFIG_MEM_TRAIN_SEQ == 0
 static int dqs_save_MC_NVRAM_ch(unsigned int dev, int ch, int pos)
 {
        /* 30 bytes per channel */
@@ -1902,6 +1896,7 @@ static void dqs_save_MC_NVRAM(unsigned int dev)
        reg = pci_read_config32(dev, DRAM_CONFIG_HIGH);
        pos = s3_save_nvram_early(reg, 4, pos);
 }
+#endif
 
 static void dqs_restore_MC_NVRAM(unsigned int dev)
 {
@@ -1917,6 +1912,7 @@ static void dqs_restore_MC_NVRAM(unsigned int dev)
        reg |= pci_read_config32(dev, DRAM_CONFIG_HIGH);
        pci_write_config32(dev, DRAM_CONFIG_HIGH, reg);
 }
+#endif
 
 #if CONFIG_MEM_TRAIN_SEQ == 0
 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
@@ -1952,7 +1948,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc
 
                printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass1: %02x\n", i);
                if(train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out;
-                       printk(BIOS_DEBUG, " done\r\n");
+                       printk(BIOS_DEBUG, " done\n");
        }
 
        tsc[1] = rdtsc();
@@ -1970,7 +1966,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc
 
                printk(BIOS_DEBUG, "DQS Training:DQSPos: %02x\n", i);
                if(train_DqsPos(ctrl+i, sysinfo)) goto out;
-               printk(BIOS_DEBUG, " done\r\n");
+               printk(BIOS_DEBUG, " done\n");
        }
 
        tsc[3] = rdtsc();
@@ -1983,9 +1979,11 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc
 
                printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass2: %02x\n", i);
                if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out;
-               printk(BIOS_DEBUG, " done\r\n");
+               printk(BIOS_DEBUG, " done\n");
                sysinfo->mem_trained[i]=1;
+#if CONFIG_HAVE_ACPI_RESUME == 1
                dqs_save_MC_NVRAM((ctrl+i)->f2);
+#endif
        }
 
 out:
@@ -2033,7 +2031,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info
        }
 
        if(v) {
-               printk(BIOS_DEBUG, " done\r\n");
+               printk(BIOS_DEBUG, " done\n");
                tsc[1] = rdtsc();
                printk(BIOS_DEBUG, "set DQS timing:DQSPos: %02x\n", i);
        }
@@ -2044,7 +2042,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info
        }
 
        if(v) {
-               printk(BIOS_DEBUG, " done\r\n");
+               printk(BIOS_DEBUG, " done\n");
                tsc[2] = rdtsc();
 
                printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass2: %02x\n", i);
@@ -2055,7 +2053,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info
        }
 
        if(v) {
-               printk(BIOS_DEBUG, " done\r\n");
+               printk(BIOS_DEBUG, " done\n");
 
                tsc[3] = rdtsc();
        }
@@ -2087,7 +2085,7 @@ static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info
        sysinfox->mem_trained[nodeid] = sysinfo->mem_trained[nodeid];
 
 }
-static void copy_and_run_ap_code_in_car(unsigned ret_addr);
+
 static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall)
 {
        if(coreid) return; // only do it on core0