MTRR related improvements for AMD family 10h and family 0Fh systems

[coreboot.git] / src / northbridge / amd / amdk8 / raminit_f_dqs.c

diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index c56e51deb05d2dcec477c42ec24aca4a580ee10b..5303a67b322faee207b61c0120680a59f8bc60bd 100644 (file)
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -528,7 +528,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st
        unsigned is_Width128 = sysinfo->meminfo[ctrl->node_id].is_Width128;
 
 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
-       unsigned cpu_f0_f1;
+       unsigned cpu_f0_f1 = 0;
 #endif
 
        if(Pass == DQS_FIRST_PASS) {
@@ -1717,6 +1717,7 @@ static unsigned int range_to_mtrr(unsigned int reg,
        return reg;
 }
 
+#if CONFIG_MEM_TRAIN_SEQ == 1
 static void set_top_mem_ap(unsigned tom_k, unsigned tom2_k)
 {
        msr_t msr;
@@ -1730,6 +1731,7 @@ static void set_top_mem_ap(unsigned tom_k, unsigned tom2_k)
        msr.hi = (tom_k & 0xffc00000) >> 22;
        wrmsr(TOP_MEM, msr);
 }
+#endif
 
 static void setup_mtrr_dqs(unsigned tom_k, unsigned tom2_k)
 {
@@ -1802,6 +1804,7 @@ static void set_htic_bit(unsigned i, unsigned val, unsigned bit)
 }
 
 
+#if CONFIG_MEM_TRAIN_SEQ == 1
 static unsigned get_htic_bit(unsigned i, unsigned bit)
 {
        uint32_t dword;
@@ -1816,6 +1819,7 @@ static void wait_till_sysinfo_in_ram(void)
                if(get_htic_bit(0, 9)) return;
        }
 }
+#endif
 
 static void set_sysinfo_in_ram(unsigned val)
 {