MTRR related improvements for AMD family 10h and family 0Fh systems

[coreboot.git] / src / northbridge / amd / amdk8 / raminit_f_dqs.c

diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index a668c9f1e02892bd80bb5bd547938c362a87e0d2..5303a67b322faee207b61c0120680a59f8bc60bd 100644 (file)
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -436,7 +436,7 @@ static uint16_t get_exact_T1000(unsigned i)
                unsigned fid_start;
                msr = rdmsr(0xc0010015);
                fid_start = (msr.lo & (0x3f << 24));
-               
+
                index = fid_start>>25;
        }
 
@@ -528,7 +528,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st
        unsigned is_Width128 = sysinfo->meminfo[ctrl->node_id].is_Width128;
 
 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
-       unsigned cpu_f0_f1;
+       unsigned cpu_f0_f1 = 0;
 #endif
 
        if(Pass == DQS_FIRST_PASS) {
@@ -600,12 +600,12 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st
        }
 
        for ( ; (channel < 2) && (!Errors); channel++)
-       { 
-               print_debug_dqs("\tTrainRcvEn51: channel ",channel, 1); 
-               
-               /* for each rank */ 
-               /* there are four recriver pairs, loosely associated with CS */ 
-               for( receiver = 0; (receiver < 8) && (!Errors); receiver+=2) 
+       {
+               print_debug_dqs("\tTrainRcvEn51: channel ",channel, 1);
+
+               /* for each rank */
+               /* there are four recriver pairs, loosely associated with CS */
+               for( receiver = 0; (receiver < 8) && (!Errors); receiver+=2)
                {
 
                        unsigned index=(receiver>>1) * 3 + 0x10;
@@ -1717,6 +1717,7 @@ static unsigned int range_to_mtrr(unsigned int reg,
        return reg;
 }
 
+#if CONFIG_MEM_TRAIN_SEQ == 1
 static void set_top_mem_ap(unsigned tom_k, unsigned tom2_k)
 {
        msr_t msr;
@@ -1730,6 +1731,7 @@ static void set_top_mem_ap(unsigned tom_k, unsigned tom2_k)
        msr.hi = (tom_k & 0xffc00000) >> 22;
        wrmsr(TOP_MEM, msr);
 }
+#endif
 
 static void setup_mtrr_dqs(unsigned tom_k, unsigned tom2_k)
 {
@@ -1802,6 +1804,7 @@ static void set_htic_bit(unsigned i, unsigned val, unsigned bit)
 }
 
 
+#if CONFIG_MEM_TRAIN_SEQ == 1
 static unsigned get_htic_bit(unsigned i, unsigned bit)
 {
        uint32_t dword;
@@ -1816,6 +1819,7 @@ static void wait_till_sysinfo_in_ram(void)
                if(get_htic_bit(0, 9)) return;
        }
 }
+#endif
 
 static void set_sysinfo_in_ram(unsigned val)
 {
@@ -1823,15 +1827,18 @@ static void set_sysinfo_in_ram(unsigned val)
 }
 
 #ifdef S3_NVRAM_EARLY
-int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
-int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
+// Don't define these prototypes as the real functions are already included
+// at this point.
+//
+//int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
+//int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 #else
-static int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
+static inline int s3_save_nvram_early(u32 dword, int size, int  nvram_pos)
 {
        return nvram_pos;
 }
 
-static int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
+static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
 {
        die("No memory NVRAM loader for DQS data! Unable to restore memory state\n");