+/* This should be done by Eric
+ 2004.12 yhlu add dual core support
+ 2005.01 yhlu add support move apic before pci_domain in MB Config.lb
+ 2005.02 yhlu add e0 memory hole support
+*/
+
#include <console/console.h>
#include <arch/io.h>
#include <stdint.h>
-#include <mem.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <string.h>
#include <bitops.h>
#include <cpu/cpu.h>
+
+#include <cpu/x86/lapic.h>
+
+#if CONFIG_LOGICAL_CPUS==1
+#include <cpu/amd/dualcore.h>
+#include <pc80/mc146818rtc.h>
+#endif
+
#include "chip.h"
+#include "root_complex/chip.h"
#include "northbridge.h"
#include "amdk8.h"
-#define DEVICE_MEM_HIGH 0xFEC00000ULL /* Reserve 20M for the system */
-#define DEVICE_IO_START 0x1000
+#if K8_E0_MEM_HOLE_SIZEK != 0
+#include "./cpu_rev.c"
+#endif
#define FX_DEVS 8
static device_t __f0_dev[FX_DEVS];
if (!(link_type & NonCoherent)) {
continue;
}
- /* See if there is an available configuration space mapping register in function 1. */
+ /* See if there is an available configuration space mapping
+ * register in function 1.
+ */
free_reg = 0;
for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
uint32_t config;
if (free_reg && (config_reg > 0xec)) {
config_reg = free_reg;
}
- /* If we can't find an available configuration space mapping register skip this bus */
+ /* If we can't find an available configuration space mapping
+ * register skip this bus
+ */
if (config_reg > 0xec) {
continue;
}
- /* Set up the primary, secondary and subordinate bus numbers. We have
- * no idea how many busses are behind this bridge yet, so we set the subordinate
- * bus number to 0xff for the moment.
+ /* Set up the primary, secondary and subordinate bus numbers.
+ * We have no idea how many busses are behind this bridge yet,
+ * so we set the subordinate bus number to 0xff for the moment.
*/
dev->link[link].secondary = ++max;
dev->link[link].subordinate = 0xff;
config_busses = f1_read_config32(config_reg);
/* Configure the bus numbers for this bridge: the configuration
- * transactions will not be propagates by the bridge if it is not
- * correctly configured
+ * transactions will not be propagates by the bridge if it is
+ * not correctly configured
*/
busses &= 0xff000000;
busses |= (((unsigned int)(dev->bus->secondary) << 0) |
#if 0
printk_debug("%s Hyper transport scan link: %d max: %d\n",
dev_path(dev), link, max);
-#endif
- /* Now we can scan all of the subordinate busses i.e. the chain on the hypertranport link */
- max = hypertransport_scan_chain(&dev->link[link], max);
+#endif
+ /* Now we can scan all of the subordinate busses i.e. the
+ * chain on the hypertranport link
+ */
+ max = hypertransport_scan_chain(&dev->link[link], 0, 0xbf, max);
#if 0
printk_debug("%s Hyper transport scan link: %d new max: %d\n",
dev_path(dev), link, max);
#endif
- /* We know the number of busses behind this bridge. Set the subordinate
- * bus number to it's real value
+ /* We know the number of busses behind this bridge. Set the
+ * subordinate bus number to it's real value
*/
dev->link[link].subordinate = max;
busses = (busses & 0xff00ffff) |
((unsigned int) (dev->link[link].subordinate) << 16);
pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
- config_busses = (config_busses & 0x00ffffff) | (dev->link[link].subordinate << 24);
+ config_busses = (config_busses & 0x00ffffff) |
+ (dev->link[link].subordinate << 24);
f1_write_config32(config_reg, config_busses);
+
#if 0
printk_debug("%s Hypertransport scan link: %d done\n",
dev_path(dev), link);
-#endif
+#endif
}
#if 0
printk_debug("%s amdk8_scan_chains max: %d done\n",
return result;
}
-
static struct resource *amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link)
{
struct resource *resource;
}
return resource;
}
+
static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
{
struct resource *resource;
limit |= (nodeid & 7);
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
+ printk_spew("%s, enabling legacy VGA IO forwarding for %s link %s\n",
+ __func__, dev_path(dev), link);
base |= PCI_IO_BASE_VGA_EN;
}
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
report_resource_stored(dev, resource, buf);
}
+/**
+ *
+ * I tried to reuse the resource allocation code in amdk8_set_resource()
+ * but it is too diffcult to deal with the resource allocation magic.
+ */
+static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
+{
+ struct resource *resource;
+ unsigned link;
+ uint32_t base, limit;
+ unsigned reg;
+
+ /* find out which link the VGA card is connected,
+ * we only deal with the 'first' vga card */
+ for (link = 0; link < dev->links; link++) {
+ if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
+ break;
+ }
+ }
+
+ printk_spew("%s: link %d has VGA device\n", __func__, link);
+
+ /* no VGA card installed */
+ if (link == dev->links)
+ return;
+
+ /* allocate a temp resrouce for legacy VGA buffer */
+ resource = amdk8_find_mempair(dev, nodeid, link);
+ resource->base = 0xa0000;
+ resource->size = 0x20000;
+
+ /* write the resource to the hardware */
+ reg = resource->index & 0xfc;
+ base = f1_read_config32(reg);
+ limit = f1_read_config32(reg + 0x4);
+ base &= 0x000000f0;
+ base |= (resource->base >> 8) & 0xffffff00;
+ base |= 3;
+ limit &= 0x00000048;
+ limit |= ((resource->base + resource->size) >> 8) & 0xffffff00;
+ limit |= (resource->index & 3) << 4;
+ limit |= (nodeid & 7);
+ f1_write_config32(reg + 0x4, limit);
+ f1_write_config32(reg, base);
+
+ /* release the temp resource */
+ resource->flags = 0;
+
+}
+
static void amdk8_set_resources(device_t dev)
{
unsigned nodeid, link;
int i;
/* Find the nodeid */
- nodeid = amdk8_nodeid(dev);
+ nodeid = amdk8_nodeid(dev);
+ amdk8_create_vga_resource(dev, nodeid);
+
/* Set each resource we have found */
for(i = 0; i < dev->resources; i++) {
amdk8_set_resource(dev, &dev->resource[i], nodeid);
}
-
+
for(link = 0; link < dev->links; link++) {
struct bus *bus;
bus = &dev->link[link];
static void mcf0_control_init(struct device *dev)
{
- uint32_t cmd;
-
#if 0
printk_debug("NB: Function 0 Misc Control.. ");
#endif
-#if 1
- /* improve latency and bandwith on HT */
- cmd = pci_read_config32(dev, 0x68);
- cmd &= 0xffff80ff;
- cmd |= 0x00004800;
- pci_write_config32(dev, 0x68, cmd );
-#endif
-
-#if 0
- /* over drive the ht port to 1000 Mhz */
- cmd = pci_read_config32(dev, 0xa8);
- cmd &= 0xfffff0ff;
- cmd |= 0x00000600;
- pci_write_config32(dev, 0xdc, cmd );
-#endif
+#if 0
printk_debug("done.\n");
+#endif
}
static struct device_operations northbridge_operations = {
.device = 0x1100,
};
+#if CONFIG_CHIP_NAME == 1
-#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH)
+struct chip_operations northbridge_amd_amdk8_ops = {
+ CHIP_NAME("AMD K8 Northbridge")
+ .enable_dev = 0,
+};
+
+#endif
static void pci_domain_read_resources(device_t dev)
{
}
/* Initialize the system wide io space constraints */
- resource = new_resource(dev, 0);
+ resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
resource->base = 0x400;
resource->limit = 0xffffUL;
- resource->flags = IORESOURCE_IO;
- compute_allocate_resource(&dev->link[0], resource,
- IORESOURCE_IO, IORESOURCE_IO);
+ resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
- /* Initialize the system wide prefetchable memory resources constraints */
- resource = new_resource(dev, 1);
- resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
- compute_allocate_resource(&dev->link[0], resource,
- IORESOURCE_MEM | IORESOURCE_PREFETCH,
- IORESOURCE_MEM | IORESOURCE_PREFETCH);
-
/* Initialize the system wide memory resources constraints */
- resource = new_resource(dev, 2);
+ resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->limit = 0xfcffffffffULL;
- resource->flags = IORESOURCE_MEM;
- compute_allocate_resource(&dev->link[0], resource,
- IORESOURCE_MEM | IORESOURCE_PREFETCH,
- IORESOURCE_MEM);
+ resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(device_t dev, unsigned long index,
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
+static void tolm_test(void *gp, struct device *dev, struct resource *new)
+{
+ struct resource **best_p = gp;
+ struct resource *best;
+ best = *best_p;
+ if (!best || (best->base > new->base)) {
+ best = new;
+ }
+ *best_p = best;
+}
+
+static uint32_t find_pci_tolm(struct bus *bus)
+{
+ struct resource *min;
+ uint32_t tolm;
+ min = 0;
+ search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
+ tolm = 0xffffffffUL;
+ if (min && tolm > min->base) {
+ tolm = min->base;
+ }
+ return tolm;
+}
+
static void pci_domain_set_resources(device_t dev)
{
- struct resource *io, *mem1, *mem2;
- struct resource *resource, *last;
unsigned long mmio_basek;
uint32_t pci_tolm;
int i, idx;
-#if 0
- /* Place the IO devices somewhere safe */
- io = find_resource(dev, 0);
- io->base = DEVICE_IO_START;
-#endif
-#if 1
- /* Now reallocate the pci resources memory with the
- * highest addresses I can manage.
- */
- mem1 = find_resource(dev, 1);
- mem2 = find_resource(dev, 2);
- /* See if both resources have roughly the same limits */
- if (((mem1->limit <= 0xffffffff) && (mem2->limit <= 0xffffffff)) ||
- ((mem1->limit > 0xffffffff) && (mem2->limit > 0xffffffff)))
- {
- /* If so place the one with the most stringent alignment first
- */
- if (mem2->align > mem1->align) {
- struct resource *tmp;
- tmp = mem1;
- mem1 = mem2;
- mem2 = mem1;
- }
- /* Now place the memory as high up as it will go */
- mem2->base = resource_max(mem2);
- mem1->limit = mem2->base - 1;
- mem1->base = resource_max(mem1);
- }
- else {
- /* Place the resources as high up as they will go */
- mem2->base = resource_max(mem2);
- mem1->base = resource_max(mem1);
- }
-
-#if 0
- printk_debug("base1: 0x%08Lx limit1: 0x%08lx size: 0x%08Lx\n",
- mem1->base, mem1->limit, mem1->size);
- printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx\n",
- mem2->base, mem2->limit, mem2->size);
-#endif
-#endif
- pci_tolm = 0xffffffffUL;
- last = &dev->resource[dev->resources];
- for(resource = &dev->resource[0]; resource < last; resource++)
- {
-#if 1
- resource->flags |= IORESOURCE_ASSIGNED;
- resource->flags &= ~IORESOURCE_STORED;
-#endif
- compute_allocate_resource(&dev->link[0], resource,
- BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
-
- resource->flags |= IORESOURCE_STORED;
- report_resource_stored(dev, resource, "");
-
- if ((resource->flags & IORESOURCE_MEM) &&
- (pci_tolm > resource->base))
- {
- pci_tolm = resource->base;
- }
- }
+ pci_tolm = find_pci_tolm(&dev->link[0]);
#warning "FIXME handle interleaved nodes"
mmio_basek = pci_tolm >> 10;
mmio_basek &= ~((64*1024) - 1);
#endif
+#if K8_E0_MEM_HOLE_SIZEK != 0
+ if (!is_cpu_pre_e0())
+ for (i = 0; i < 8; i++) {
+ uint32_t base;
+ base = f1_read_config32(0x40 + (i << 3));
+ if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
+ continue;
+ }
+
+ base = pci_read_config32(__f1_dev[i], 0xf0);
+ if((base & 1)==0) continue;
+ base &= 0xff<<24;
+ base >>= 10;
+ if (mmio_basek > base) {
+ mmio_basek = base;
+ }
+ break; // only one hole
+ }
+#endif
+
idx = 10;
for(i = 0; i < 8; i++) {
uint32_t base, limit;
}
ram_resource(dev, idx++, basek, sizek);
}
-
assign_resources(&dev->link[0]);
}
f1_write_config32(reg, 0);
}
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max);
+
+ /* Tune the hypertransport transaction for best performance.
+ * Including enabling relaxed ordering if it is safe.
+ */
+ get_fx_devs();
+ for(i = 0; i < FX_DEVS; i++) {
+ device_t f0_dev;
+ f0_dev = __f0_dev[i];
+ if (f0_dev && f0_dev->enabled) {
+ uint32_t httc;
+ int j;
+ httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL);
+ httc &= ~HTTC_RSP_PASS_PW;
+ if (!dev->link[0].disable_relaxed_ordering) {
+ httc |= HTTC_RSP_PASS_PW;
+ }
+ printk_spew("%s passpw: %s\n",
+ dev_path(dev),
+ (!dev->link[0].disable_relaxed_ordering)?
+ "enabled":"disabled");
+ pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc);
+ }
+ }
return max;
}
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = pci_domain_scan_bus,
+ .ops_pci_bus = &pci_cf8_conf1,
};
+#define APIC_ID_OFFSET 0x10
+
static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
{
struct bus *cpu_bus;
- unsigned reg;
- int i;
+ device_t dev_mc;
+ int bsp_apic_id;
+ int apic_id_offset;
+ int i,j;
+ unsigned nb_cfg_54;
+ int enable_apic_ext_id;
+ unsigned siblings;
+#if CONFIG_LOGICAL_CPUS == 1
+ int e0_later_single_core;
+ int disable_siblings;
+#endif
+
+ nb_cfg_54 = 0;
+ enable_apic_ext_id = 0;
+ siblings = 0;
+
+ /* Find the bootstrap processors apicid */
+ bsp_apic_id = lapicid();
+
+ /* See if I will enable extended ids' */
+ apic_id_offset = bsp_apic_id;
+
+#if CONFIG_LOGICAL_CPUS == 1
+ disable_siblings = !CONFIG_LOGICAL_CPUS;
+ get_option(&disable_siblings, "dual_core");
+
+ // for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it still be 0)
+ // How can I get the nb_cfg_54 of every node' nb_cfg_54 in bsp??? and differ d0 and e0 single core
+
+ nb_cfg_54 = read_nb_cfg_54();
+#endif
+ dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
+ if (!dev_mc) {
+ die("0:18.0 not found?");
+ }
+ if (pci_read_config32(dev_mc, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST))
+ {
+ enable_apic_ext_id = 1;
+ if (apic_id_offset == 0) {
+ /* bsp apic id is not changed */
+ apic_id_offset = APIC_ID_OFFSET;
+ }
+ }
/* Find which cpus are present */
cpu_bus = &dev->link[0];
- for(i = 0; i < 7; i++) {
+ for(i = 0; i < 8; i++) {
device_t dev, cpu;
struct device_path cpu_path;
- /* Find the cpu's memory controller */
- dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
-
- /* Build the cpu device path */
- cpu_path.type = DEVICE_PATH_APIC;
- cpu_path.u.apic.apic_id = i;
+ /* Find the cpu's pci device */
+ dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
+ if (!dev) {
+ /* If I am probing things in a weird order
+ * ensure all of the cpu's pci devices are found.
+ */
+ int j;
+ for(j = 0; j <= 3; j++) {
+ dev = pci_probe_dev(NULL, dev_mc->bus,
+ PCI_DEVFN(0x18 + i, j));
+ }
+ }
- /* See if I can find the cpu */
- cpu = find_dev_path(cpu_bus, &cpu_path);
+#if CONFIG_LOGICAL_CPUS == 1
+ e0_later_single_core = 0;
+ if ((!disable_siblings) && dev && dev->enabled) {
+ j = (pci_read_config32(dev, 0xe8) >> 12) & 3; // dev is func 3
+ printk_debug(" %s siblings=%d\r\n", dev_path(dev), j);
+
+ if(nb_cfg_54) {
+ // For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4....
+ // ----> you can mixed single core e0 and dual core e0 at any sequence
+ // That is the typical case
+
+ if(j == 0 ){
+ e0_later_single_core = is_e0_later_in_bsp(i); // single core
+ } else {
+ e0_later_single_core = 0;
+ }
+ if(e0_later_single_core) {
+ printk_debug("\tFound e0 single core\r\n");
+ j=1;
+ }
+
+ if(siblings > j ) {
+ //actually we can't be here, because d0 nb_cfg_54 can not be set
+ //even worse is_e0_later_in_bsp() can not find out if it is d0 or e0
- /* Enable the cpu if I have the processor */
- if (dev && dev->enabled) {
- if (!cpu) {
- cpu = alloc_dev(cpu_bus, &cpu_path);
+ die("When NB_CFG_54 is set, if you want to mix e0 (single core and dual core) and single core(pre e0) CPUs, you need to put all the single core (pre e0) CPUs before all the (e0 single or dual core) CPUs\r\n");
+ }
+ else {
+ siblings = j;
+ }
+ } else {
+ siblings = j;
+ }
+ }
+#endif
+#if CONFIG_LOGICAL_CPUS==1
+ for (j = 0; j <= (e0_later_single_core?0:siblings); j++ ) {
+#else
+ for (j = 0; j <= siblings; j++ ) {
+#endif
+ /* Build the cpu device path */
+ cpu_path.type = DEVICE_PATH_APIC;
+ cpu_path.u.apic.apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
+
+ /* See if I can find the cpu */
+ cpu = find_dev_path(cpu_bus, &cpu_path);
+
+ /* Enable the cpu if I have the processor */
+ if (dev && dev->enabled) {
+ if (!cpu) {
+ cpu = alloc_dev(cpu_bus, &cpu_path);
+ }
+ if (cpu) {
+ cpu->enabled = 1;
+ }
+ }
+
+ /* Disable the cpu if I don't have the processor */
+ if (cpu && (!dev || !dev->enabled)) {
+ cpu->enabled = 0;
}
+
+ /* Report what I have done */
if (cpu) {
- cpu->enabled = 1;
+ if(enable_apic_ext_id) {
+ if(cpu->path.u.apic.apic_id<apic_id_offset) { //all add offset except bsp core0
+ if( (cpu->path.u.apic.apic_id > siblings) || (bsp_apic_id!=0) )
+ cpu->path.u.apic.apic_id += apic_id_offset;
+ }
+ }
+ printk_debug("CPU: %s %s\n",
+ dev_path(cpu), cpu->enabled?"enabled":"disabled");
}
- }
-
- /* Disable the cpu if I don't have the processor */
- if (cpu && (!dev || !dev->enabled)) {
- cpu->enabled = 0;
- }
-
- /* Report what I have done */
- if (cpu) {
- printk_debug("CPU: %s %s\n",
- dev_path(cpu), cpu->enabled?"enabled":"disabled");
- }
+ } //j
}
return max;
}
.read_resources = cpu_bus_noop,
.set_resources = cpu_bus_noop,
.enable_resources = cpu_bus_noop,
- .init = cpu_bus_init,
+ .init = cpu_bus_init,
.scan_bus = cpu_bus_scan,
};
-static void enable_dev(struct device *dev)
+static void root_complex_enable_dev(struct device *dev)
{
- struct device_path path;
-
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
dev->ops = &pci_domain_ops;
}
}
-struct chip_operations northbridge_amd_amdk8_ops = {
- .name = "AMD K8 Northbridge",
- .enable_dev = enable_dev,
+struct chip_operations northbridge_amd_amdk8_root_complex_ops = {
+ CHIP_NAME("AMD K8 Root Complex")
+ .enable_dev = root_complex_enable_dev,
};
projects / coreboot.git / blobdiff