struct amdk8_sysconf_t sysconf;
-#define FX_DEVS 8
-static device_t __f0_dev[FX_DEVS];
-static device_t __f1_dev[FX_DEVS];
-
-#if 0
-static void debug_fx_devs(void)
-{
- int i;
- for(i = 0; i < FX_DEVS; i++) {
- device_t dev;
- dev = __f0_dev[i];
- if (dev) {
- printk_debug("__f0_dev[%d]: %s bus: %p\n",
- i, dev_path(dev), dev->bus);
- }
- dev = __f1_dev[i];
- if (dev) {
- printk_debug("__f1_dev[%d]: %s bus: %p\n",
- i, dev_path(dev), dev->bus);
- }
- }
-}
-#endif
+#define MAX_FX_DEVS 8
+static device_t __f0_dev[MAX_FX_DEVS];
+static device_t __f1_dev[MAX_FX_DEVS];
+static unsigned fx_devs=0;
static void get_fx_devs(void)
{
int i;
- if (__f1_dev[0]) {
- return;
- }
- for(i = 0; i < FX_DEVS; i++) {
+ for(i = 0; i < MAX_FX_DEVS; i++) {
__f0_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
__f1_dev[i] = dev_find_slot(0, PCI_DEVFN(0x18 + i, 1));
+ if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
+ fx_devs = i+1;
}
- if (!__f1_dev[0]) {
- die("Cannot find 0:0x18.1\n");
+ if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) {
+ die("Cannot find 0:0x18.[0|1]\n");
}
}
static uint32_t f1_read_config32(unsigned reg)
{
- get_fx_devs();
+ if ( fx_devs == 0)
+ get_fx_devs();
return pci_read_config32(__f1_dev[0], reg);
}
static void f1_write_config32(unsigned reg, uint32_t value)
{
int i;
- get_fx_devs();
- for(i = 0; i < FX_DEVS; i++) {
+ if ( fx_devs == 0)
+ get_fx_devs();
+ for(i = 0; i < fx_devs; i++) {
device_t dev;
dev = __f1_dev[i];
if (dev && dev->enabled) {
unsigned nodeid, link=0;
int result;
res = 0;
- for(nodeid = 0; !res && (nodeid < FX_DEVS); nodeid++) {
+ for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
device_t dev;
dev = __f0_dev[nodeid];
if (!dev)
return result;
}
-static struct resource *amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link)
+static unsigned amdk8_find_reg(device_t dev, unsigned nodeid, unsigned link,
+ unsigned min, unsigned max)
{
- struct resource *resource;
+ unsigned resource;
unsigned free_reg, reg;
resource = 0;
free_reg = 0;
- for(reg = 0xc0; reg <= 0xd8; reg += 0x8) {
+ for(reg = min; reg <= max; reg += 0x8) {
int result;
result = reg_useable(reg, dev, nodeid, link);
if (result == 1) {
free_reg = reg;
}
}
- if (reg > 0xd8) {
+ if (reg > max) {
reg = free_reg;
}
if (reg > 0) {
- resource = new_resource(dev, IOINDEX(0x100 + reg, link));
+ resource = IOINDEX(0x100 + reg, link);
}
return resource;
}
-static struct resource *amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link)
+static unsigned amdk8_find_iopair(device_t dev, unsigned nodeid, unsigned link)
{
- struct resource *resource;
- unsigned free_reg, reg;
- resource = 0;
- free_reg = 0;
- for(reg = 0x80; reg <= 0xb8; reg += 0x8) {
- int result;
- result = reg_useable(reg, dev, nodeid, link);
- if (result == 1) {
- /* I have been allocated this one */
- break;
- }
- else if (result > 1) {
- /* I have a free register pair */
- free_reg = reg;
- }
- }
- if (reg > 0xb8) {
- reg = free_reg;
- }
- if (reg > 0) {
- resource = new_resource(dev, IOINDEX(0x100 + reg, link));
- }
- return resource;
+ return amdk8_find_reg(dev, nodeid, link, 0xc0, 0xd8);
+}
+
+static unsigned amdk8_find_mempair(device_t dev, unsigned nodeid, unsigned link)
+{
+ return amdk8_find_reg(dev, nodeid, link, 0x80, 0xb8);
}
static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
struct resource *resource;
/* Initialize the io space constraints on the current bus */
- resource = amdk8_find_iopair(dev, nodeid, link);
+ resource = new_resource(dev, IOINDEX(0, link));
if (resource) {
resource->base = 0;
resource->size = 0;
}
/* Initialize the prefetchable memory constraints on the current bus */
- resource = amdk8_find_mempair(dev, nodeid, link);
+ resource = new_resource(dev, IOINDEX(2, link));
if (resource) {
resource->base = 0;
resource->size = 0;
resource->gran = log2(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-#ifdef CONFIG_PCI_64BIT_PREF_MEM
resource->flags |= IORESOURCE_BRIDGE;
-#endif
}
/* Initialize the memory constraints on the current bus */
- resource = amdk8_find_mempair(dev, nodeid, link);
+ resource = new_resource(dev, IOINDEX(1, link));
if (resource) {
resource->base = 0;
resource->size = 0;
}
}
+static void amdk8_create_vga_resource(device_t dev, unsigned nodeid);
+
static void amdk8_read_resources(device_t dev)
{
unsigned nodeid, link;
amdk8_link_read_bases(dev, nodeid, link);
}
}
+
+ amdk8_create_vga_resource(dev, nodeid);
}
static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid)
/* Make certain the resource has actually been set */
if (!(resource->flags & IORESOURCE_ASSIGNED)) {
- printk_err("%s: can't set unassigned resource @%lx %lx\n",
+ printk(BIOS_ERR, "%s: can't set unassigned resource @%lx %lx\n",
__func__, resource->index, resource->flags);
return;
}
/* If I have already stored this resource don't worry about it */
if (resource->flags & IORESOURCE_STORED) {
- printk_err("%s: can't set stored resource @%lx %lx\n", __func__,
+ printk(BIOS_ERR, "%s: can't set stored resource @%lx %lx\n", __func__,
resource->index, resource->flags);
return;
}
limit |= (nodeid & 7);
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
- printk_spew("%s, enabling legacy VGA IO forwarding for %s link 0x%x\n",
+ printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link 0x%x\n",
__func__, dev_path(dev), link);
base |= PCI_IO_BASE_VGA_EN;
}
report_resource_stored(dev, resource, buf);
}
-/**
- *
- * I tried to reuse the resource allocation code in amdk8_set_resource()
- * but it is too diffcult to deal with the resource allocation magic.
- */
#if CONFIG_CONSOLE_VGA_MULTI == 1
extern device_t vga_pri; // the primary vga device, defined in device.c
#endif
{
struct resource *resource;
unsigned link;
- uint32_t base, limit;
- unsigned reg;
/* find out which link the VGA card is connected,
* we only deal with the 'first' vga card */
for (link = 0; link < dev->links; link++) {
if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
#if CONFIG_CONSOLE_VGA_MULTI == 1
- printk_debug("VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
+ printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
dev->link[link].secondary,dev->link[link].subordinate);
/* We need to make sure the vga_pri is under the link */
if((vga_pri->bus->secondary >= dev->link[link].secondary ) &&
if (link == dev->links)
return;
- printk_debug("VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link);
+ printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link);
- /* allocate a temp resrouce for legacy VGA buffer */
- resource = amdk8_find_mempair(dev, nodeid, link);
+ /* allocate a temp resource for the legacy VGA buffer */
+ resource = new_resource(dev, IOINDEX(4, link));
if(!resource){
- printk_debug("VGA: Can not find free mmio reg for legacy VGA buffer\n");
+ printk(BIOS_DEBUG, "VGA: %s out of resources.\n", dev_path(dev));
return;
}
resource->base = 0xa0000;
resource->size = 0x20000;
-
- /* write the resource to the hardware */
- reg = resource->index & 0xfc;
- base = f1_read_config32(reg);
- limit = f1_read_config32(reg + 0x4);
- base &= 0x000000f0;
- base |= (resource->base >> 8) & 0xffffff00;
- base |= 3;
- limit &= 0x00000048;
- limit |= (resource_end(resource) >> 8) & 0xffffff00;
- limit |= (resource->index & 3) << 4;
- limit |= (nodeid & 7);
- f1_write_config32(reg + 0x4, limit);
- f1_write_config32(reg, base);
-
- /* release the temp resource */
- resource->flags = 0;
+ resource->limit = 0xffffffff;
+ resource->flags = IORESOURCE_FIXED | IORESOURCE_MEM |
+ IORESOURCE_ASSIGNED;
}
static void amdk8_set_resources(device_t dev)
/* Find the nodeid */
nodeid = amdk8_nodeid(dev);
- amdk8_create_vga_resource(dev, nodeid);
-
/* Set each resource we have found */
for(i = 0; i < dev->resources; i++) {
- amdk8_set_resource(dev, &dev->resource[i], nodeid);
+ struct resource *res = &dev->resource[i];
+ struct resource *old = NULL;
+ unsigned index;
+
+ if (res->size == 0) /* No need to allocate registers. */
+ continue;
+
+ if (res->flags & IORESOURCE_IO)
+ index = amdk8_find_iopair(dev, nodeid,
+ IOINDEX_LINK(res->index));
+ else
+ index = amdk8_find_mempair(dev, nodeid,
+ IOINDEX_LINK(res->index));
+
+ old = probe_resource(dev, index);
+ if (old) {
+ res->index = old->index;
+ old->index = 0;
+ old->flags = 0;
+ }
+ else
+ res->index = index;
+
+ amdk8_set_resource(dev, res, nodeid);
}
+ compact_resources(dev);
+
for(link = 0; link < dev->links; link++) {
struct bus *bus;
bus = &dev->link[link];
static void mcf0_control_init(struct device *dev)
{
#if 0
- printk_debug("NB: Function 0 Misc Control.. ");
+ printk(BIOS_DEBUG, "NB: Function 0 Misc Control.. ");
#endif
#if 0
- printk_debug("done.\n");
+ printk(BIOS_DEBUG, "done.\n");
#endif
}
static void amdk8_domain_read_resources(device_t dev)
{
- struct resource *resource;
unsigned reg;
/* Find the already assigned resource pairs */
reg_dev = __f0_dev[nodeid];
if (reg_dev) {
/* Reserve the resource */
- struct resource *reg_resource;
- reg_resource = new_resource(reg_dev, IOINDEX(0x100 + reg, link));
- if (reg_resource) {
- reg_resource->flags = 1;
+ struct resource *res;
+ res = new_resource(reg_dev, IOINDEX(0x100 + reg, link));
+ if (res) {
+ res->base = base;
+ res->limit = limit;
+ res->flags = 1;
}
}
}
struct resource **best_p = gp;
struct resource *best;
best = *best_p;
- if (!best || (best->base > new->base)) {
+ /* Skip VGA. */
+ if (!best || (best->base > new->base && new->base > 0xa0000)) {
best = new;
}
*best_p = best;
mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
mem_hole.node_id = -1;
- for (i = 0; i < FX_DEVS; i++) {
+ for (i = 0; i < fx_devs; i++) {
uint32_t base;
uint32_t hole;
base = f1_read_config32(0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
- if (!__f1_dev[i])
- continue;
+
hole = pci_read_config32(__f1_dev[i], 0xf0);
if(hole & 1) { // we find the hole
mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
return mem_hole;
}
-static void disable_hoist_memory(unsigned long hole_startk, int i)
+
+static void disable_hoist_memory(unsigned long hole_startk, int node_id)
{
- int ii;
+ int i;
device_t dev;
uint32_t base, limit;
uint32_t hoist;
hole_sizek = (4*1024*1024) - hole_startk;
- for(ii=7;ii>i;ii--) {
+ for(i=7;i>node_id;i--) {
- base = f1_read_config32(0x40 + (ii << 3));
+ base = f1_read_config32(0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
- limit = f1_read_config32(0x44 + (ii << 3));
- f1_write_config32(0x44 + (ii << 3),limit - (hole_sizek << 2));
- f1_write_config32(0x40 + (ii << 3),base - (hole_sizek << 2));
+ limit = f1_read_config32(0x44 + (i << 3));
+ f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
+ f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2));
}
- limit = f1_read_config32(0x44 + (i << 3));
- f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
- dev = __f1_dev[i];
- if (dev) {
- hoist = pci_read_config32(dev, 0xf0);
- if(hoist & 1) {
- pci_write_config32(dev, 0xf0, 0);
- } else {
- base = pci_read_config32(dev, 0x40 + (i << 3));
- f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2));
- }
+ limit = f1_read_config32(0x44 + (node_id << 3));
+ f1_write_config32(0x44 + (node_id << 3),limit - (hole_sizek << 2));
+ dev = __f1_dev[node_id];
+ if (dev == NULL) {
+ printk(BIOS_ERR, "%s: node %x is NULL!\n", __func__, node_id);
+ return;
+ }
+ hoist = pci_read_config32(dev, 0xf0);
+ if(hoist & 1)
+ pci_write_config32(dev, 0xf0, 0);
+ else {
+ base = pci_read_config32(dev, 0x40 + (node_id << 3));
+ f1_write_config32(0x40 + (node_id << 3),base - (hole_sizek << 2));
}
}
-static uint32_t hoist_memory(unsigned long hole_startk, int i)
+static uint32_t hoist_memory(unsigned long hole_startk, int node_id)
{
- int ii;
+ int i;
uint32_t carry_over;
device_t dev;
uint32_t base, limit;
carry_over = (4*1024*1024) - hole_startk;
- for(ii=7;ii>i;ii--) {
+ for(i=7;i>node_id;i--) {
- base = f1_read_config32(0x40 + (ii << 3));
+ base = f1_read_config32(0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
- limit = f1_read_config32(0x44 + (ii << 3));
- f1_write_config32(0x44 + (ii << 3),limit + (carry_over << 2));
- f1_write_config32(0x40 + (ii << 3),base + (carry_over << 2));
+ limit = f1_read_config32(0x44 + (i << 3));
+ f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
+ f1_write_config32(0x40 + (i << 3),base + (carry_over << 2));
}
- limit = f1_read_config32(0x44 + (i << 3));
- f1_write_config32(0x44 + (i << 3),limit + (carry_over << 2));
- dev = __f1_dev[i];
- base = pci_read_config32(dev, 0x40 + (i << 3));
+ limit = f1_read_config32(0x44 + (node_id << 3));
+ f1_write_config32(0x44 + (node_id << 3),limit + (carry_over << 2));
+ dev = __f1_dev[node_id];
+ base = pci_read_config32(dev, 0x40 + (node_id << 3));
basek = (base & 0xffff0000) >> 2;
if(basek == hole_startk) {
//don't need set memhole here, because hole off set will be 0, overflow
//so need to change base reg instead, new basek will be 4*1024*1024
base &= 0x0000ffff;
base |= (4*1024*1024)<<2;
- f1_write_config32(0x40 + (i<<3), base);
+ f1_write_config32(0x40 + (node_id<<3), base);
}
else if (dev)
{
}
#endif
-#if CONFIG_HAVE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES==1
#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
extern uint64_t high_tables_base, high_tables_size;
+#if CONFIG_GFXUMA == 1
+extern uint64_t uma_memory_base, uma_memory_size;
+#endif
#endif
static void amdk8_domain_set_resources(device_t dev)
mem2 = find_resource(dev, 2);
#if 1
- printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
+ printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
- printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
+ printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
#endif
}
#if 1
- printk_debug("base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
+ printk(BIOS_DEBUG, "base1: 0x%08Lx limit1: 0x%08Lx size: 0x%08Lx align: %d\n",
mem1->base, mem1->limit, mem1->size, mem1->align);
- printk_debug("base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
+ printk(BIOS_DEBUG, "base2: 0x%08Lx limit2: 0x%08Lx size: 0x%08Lx align: %d\n",
mem2->base, mem2->limit, mem2->size, mem2->align);
#endif
#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
//We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
uint32_t basek_pri;
- for (i = 0; i < FX_DEVS; i++) {
+ for (i = 0; i < fx_devs; i++) {
uint32_t base;
uint32_t basek;
base = f1_read_config32(0x40 + (i << 3));
#endif
idx = 0x10;
- for(i = 0; i < FX_DEVS; i++) {
+ for(i = 0; i < fx_devs; i++) {
uint32_t base, limit;
unsigned basek, limitk, sizek;
base = f1_read_config32(0x40 + (i << 3));
}
-// printk_debug("node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu
+#if CONFIG_GFXUMA == 1
+ printk(BIOS_DEBUG, "node %d : uma_memory_base/1024=0x%08x, mmio_basek=0x%08x, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk);
+ if ((uma_memory_base >> 10) < mmio_basek)
+ printk(BIOS_ALERT, "node %d: UMA memory starts below mmio_basek\n", i);
+#else
+// printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu
+#endif
/* See if I need to split the region to accomodate pci memory space */
if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
-#if CONFIG_HAVE_HIGH_TABLES==1
+#if CONFIG_WRITE_HIGH_TABLES==1
if (i==0 && high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
+#if CONFIG_GFXUMA == 1
+ high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
+#else
high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
+#endif
high_tables_size = HIGH_TABLES_SIZE * 1024;
- printk_debug("(split)%xK table at =%08llx\n", HIGH_TABLES_SIZE,
+ printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE,
high_tables_base);
}
#endif
if (sizek)
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
-#if CONFIG_HAVE_HIGH_TABLES==1
- printk_debug("%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
+#if CONFIG_WRITE_HIGH_TABLES==1
+ printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
i, mmio_basek, basek, limitk);
if (i==0 && high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
+#if CONFIG_GFXUMA == 1
+ high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
+#else
high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024;
+#endif
high_tables_size = HIGH_TABLES_SIZE * 1024;
}
#endif
* Including enabling relaxed ordering if it is safe.
*/
get_fx_devs();
- for(i = 0; i < FX_DEVS; i++) {
+ for(i = 0; i < fx_devs; i++) {
device_t f0_dev;
f0_dev = __f0_dev[i];
if (f0_dev && f0_dev->enabled) {
if (!dev->link[0].disable_relaxed_ordering) {
httc |= HTTC_RSP_PASS_PW;
}
- printk_spew("%s passpw: %s\n",
+ printk(BIOS_SPEW, "%s passpw: %s\n",
dev_path(dev),
(!dev->link[0].disable_relaxed_ordering)?
"enabled":"disabled");
if (cpu_dev && cpu_dev->enabled) {
j = pci_read_config32(cpu_dev, 0xe8);
j = (j >> 12) & 3; // dev is func 3
- printk_debug(" %s siblings=%d\n", dev_path(cpu_dev), j);
+ printk(BIOS_DEBUG, " %s siblings=%d\n", dev_path(cpu_dev), j);
if(nb_cfg_54) {
// For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4....
e0_later_single_core = 0;
}
if(e0_later_single_core) {
- printk_debug("\tFound Rev E or Rev F later single core\r\n");
+ printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\r\n");
j=1;
}
cpu->path.apic.apic_id += sysconf.apicid_offset;
}
}
- printk_debug("CPU: %s %s\n",
+ printk(BIOS_DEBUG, "CPU: %s %s\n",
dev_path(cpu), cpu->enabled?"enabled":"disabled");
}
projects / coreboot.git / blobdiff