}
}
-static uint32_t f1_read_config32(unsigned reg)
+static u32 f1_read_config32(unsigned reg)
{
- if ( fx_devs == 0)
+ if (fx_devs == 0)
get_fx_devs();
return pci_read_config32(__f1_dev[0], reg);
}
-static void f1_write_config32(unsigned reg, uint32_t value)
+static void f1_write_config32(unsigned reg, u32 value)
{
int i;
- if ( fx_devs == 0)
+ if (fx_devs == 0)
get_fx_devs();
for(i = 0; i < fx_devs; i++) {
device_t dev;
}
}
-static unsigned int amdk8_nodeid(device_t dev)
+static u32 amdk8_nodeid(device_t dev)
{
return (dev->path.pci.devfn >> 3) - 0x18;
}
-static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid)
+static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, u32 link_num, u32 sblink,
+ u32 max, u32 offset_unitid)
{
- uint32_t link_type;
+ u32 link_type;
int i;
- uint32_t busses, config_busses;
- unsigned free_reg, config_reg;
- unsigned ht_unitid_base[4]; // here assume only 4 HT device on chain
- unsigned max_bus;
- unsigned min_bus;
- unsigned max_devfn;
-
- dev->link[link].cap = 0x80 + (link *0x20);
+ u32 busses, config_busses;
+ u32 free_reg, config_reg;
+ u32 ht_unitid_base[4]; // here assume only 4 HT device on chain
+ u32 max_bus;
+ u32 min_bus;
+ u32 max_devfn;
+
+ link->cap = 0x80 + (link_num *0x20);
do {
- link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
+ link_type = pci_read_config32(dev, link->cap + 0x18);
} while(link_type & ConnectionPending);
if (!(link_type & LinkConnected)) {
return max;
}
do {
- link_type = pci_read_config32(dev, dev->link[link].cap + 0x18);
+ link_type = pci_read_config32(dev, link->cap + 0x18);
} while(!(link_type & InitComplete));
if (!(link_type & NonCoherent)) {
return max;
*/
free_reg = 0;
for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
- uint32_t config;
+ u32 config;
config = f1_read_config32(config_reg);
if (!free_reg && ((config & 3) == 0)) {
free_reg = config_reg;
}
if (((config & 3) == 3) &&
(((config >> 4) & 7) == nodeid) &&
- (((config >> 8) & 3) == link)) {
+ (((config >> 8) & 3) == link_num)) {
break;
}
}
*/
#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
// first chain will on bus 0
- if((nodeid == 0) && (sblink==link)) { // actually max is 0 here
+ if((nodeid == 0) && (sblink==link_num)) { // actually max is 0 here
min_bus = max;
}
#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1
max = min_bus;
#else
//other ...
- else {
+ else {
min_bus = ++max;
}
#endif
#endif
max_bus = 0xff;
- dev->link[link].secondary = min_bus;
- dev->link[link].subordinate = max_bus;
+ link->secondary = min_bus;
+ link->subordinate = max_bus;
/* Read the existing primary/secondary/subordinate bus
* number configuration.
*/
- busses = pci_read_config32(dev, dev->link[link].cap + 0x14);
+ busses = pci_read_config32(dev, link->cap + 0x14);
config_busses = f1_read_config32(config_reg);
/* Configure the bus numbers for this bridge: the configuration
*/
busses &= 0xff000000;
busses |= (((unsigned int)(dev->bus->secondary) << 0) |
- ((unsigned int)(dev->link[link].secondary) << 8) |
- ((unsigned int)(dev->link[link].subordinate) << 16));
- pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
+ ((unsigned int)(link->secondary) << 8) |
+ ((unsigned int)(link->subordinate) << 16));
+ pci_write_config32(dev, link->cap + 0x14, busses);
config_busses &= 0x000fc88;
config_busses |=
(3 << 0) | /* rw enable, no device compare */
(( nodeid & 7) << 4) |
- (( link & 3 ) << 8) |
- ((dev->link[link].secondary) << 16) |
- ((dev->link[link].subordinate) << 24);
+ (( link_num & 3 ) << 8) |
+ ((link->secondary) << 16) |
+ ((link->subordinate) << 24);
f1_write_config32(config_reg, config_busses);
/* Now we can scan all of the subordinate busses i.e. the
else
max_devfn = (0x1f<<3) | 7;
- max = hypertransport_scan_chain(&dev->link[link], 0, max_devfn, max, ht_unitid_base, offset_unitid);
+ max = hypertransport_scan_chain(link, 0, max_devfn, max, ht_unitid_base, offset_unitid);
/* We know the number of busses behind this bridge. Set the
* subordinate bus number to it's real value
*/
- dev->link[link].subordinate = max;
+ link->subordinate = max;
busses = (busses & 0xff00ffff) |
- ((unsigned int) (dev->link[link].subordinate) << 16);
- pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
+ ((unsigned int) (link->subordinate) << 16);
+ pci_write_config32(dev, link->cap + 0x14, busses);
config_busses = (config_busses & 0x00ffffff) |
- (dev->link[link].subordinate << 24);
+ (link->subordinate << 24);
f1_write_config32(config_reg, config_busses);
{
- // config config_reg, and ht_unitid_base to update hcdn_reg;
+ // use config_reg and ht_unitid_base to update hcdn_reg
int index;
- unsigned temp = 0;
+ u32 temp = 0;
index = (config_reg-0xe0) >> 2;
for(i=0;i<4;i++) {
temp |= (ht_unitid_base[i] & 0xff) << (i*8);
sysconf.hcdn_reg[index] = temp;
}
-
return max;
}
-static unsigned int amdk8_scan_chains(device_t dev, unsigned int max)
+static unsigned amdk8_scan_chains(device_t dev, unsigned max)
{
unsigned nodeid;
- unsigned link;
+ struct bus *link;
unsigned sblink = 0;
unsigned offset_unitid = 0;
+
nodeid = amdk8_nodeid(dev);
if(nodeid==0) {
#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
offset_unitid = 1;
#endif
- max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0
+ for (link = dev->link_list; link; link = link->next)
+ if (link->link_num == sblink)
+ max = amdk8_scan_chain(dev, nodeid, link, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0
#endif
}
- for(link = 0; link < dev->links; link++) {
+ for (link = dev->link_list; link; link = link->next) {
#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
- if( (nodeid == 0) && (sblink == link) ) continue; //already done
+ if( (nodeid == 0) && (sblink == link->link_num) ) continue; //already done
#endif
offset_unitid = 0;
#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
#if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
- if((nodeid == 0) && (sblink == link))
+ if((nodeid == 0) && (sblink == link->link_num))
#endif
offset_unitid = 1;
#endif
- max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid);
+ max = amdk8_scan_chain(dev, nodeid, link, link->link_num, sblink, max, offset_unitid);
}
-
return max;
}
-static int reg_useable(unsigned reg,
- device_t goal_dev, unsigned goal_nodeid, unsigned goal_link)
+static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid,
+ unsigned goal_link)
{
struct resource *res;
- unsigned nodeid, link=0;
+ unsigned nodeid, link = 0;
int result;
res = 0;
for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
result = 1;
}
}
-
return result;
}
/* Initialize the prefetchable memory constraints on the current bus */
resource = new_resource(dev, IOINDEX(2, link));
if (resource) {
- resource->base = 0;
- resource->size = 0;
+ resource->base = 0;
+ resource->size = 0;
resource->align = log2(HT_MEM_HOST_ALIGN);
- resource->gran = log2(HT_MEM_HOST_ALIGN);
+ resource->gran = log2(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
resource->flags |= IORESOURCE_BRIDGE;
/* Initialize the memory constraints on the current bus */
resource = new_resource(dev, IOINDEX(1, link));
if (resource) {
- resource->base = 0;
- resource->size = 0;
+ resource->base = 0;
+ resource->size = 0;
resource->align = log2(HT_MEM_HOST_ALIGN);
- resource->gran = log2(HT_MEM_HOST_ALIGN);
+ resource->gran = log2(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
}
static void amdk8_read_resources(device_t dev)
{
- unsigned nodeid, link;
+ unsigned nodeid;
+ struct bus *link;
nodeid = amdk8_nodeid(dev);
- for(link = 0; link < dev->links; link++) {
- if (dev->link[link].children) {
- amdk8_link_read_bases(dev, nodeid, link);
+ for(link = dev->link_list; link; link = link->next) {
+ if (link->children) {
+ amdk8_link_read_bases(dev, nodeid, link->link_num);
}
}
-
amdk8_create_vga_resource(dev, nodeid);
}
static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid)
{
+ struct bus *link;
resource_t rbase, rend;
- unsigned reg, link;
+ unsigned reg, link_num;
char buf[50];
/* Make certain the resource has actually been set */
/* Get the register and link */
reg = resource->index & 0xfc;
- link = IOINDEX_LINK(resource->index);
+ link_num = IOINDEX_LINK(resource->index);
+
+ for (link = dev->link_list; link; link = link->next)
+ if (link->link_num == link_num)
+ break;
+
+ if (link == NULL) {
+ printk(BIOS_ERR, "%s: can't find link %x for %lx\n", __func__,
+ link_num, resource->index);
+ return;
+ }
if (resource->flags & IORESOURCE_IO) {
- uint32_t base, limit;
+ u32 base, limit;
base = f1_read_config32(reg);
limit = f1_read_config32(reg + 0x4);
base &= 0xfe000fcc;
base |= 3;
limit &= 0xfe000fc8;
limit |= rend & 0x01fff000;
- limit |= (link & 3) << 4;
+ limit |= (link_num & 3) << 4;
limit |= (nodeid & 7);
- if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
+ if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
printk(BIOS_SPEW, "%s, enabling legacy VGA IO forwarding for %s link 0x%x\n",
- __func__, dev_path(dev), link);
+ __func__, dev_path(dev), link_num);
base |= PCI_IO_BASE_VGA_EN;
}
- if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
+ if (link->bridge_ctrl & PCI_BRIDGE_CTL_NO_ISA) {
base |= PCI_IO_BASE_NO_ISA;
}
f1_write_config32(reg, base);
}
else if (resource->flags & IORESOURCE_MEM) {
- uint32_t base, limit;
+ u32 base, limit;
base = f1_read_config32(reg);
limit = f1_read_config32(reg + 0x4);
base &= 0x000000f0;
base |= 3;
limit &= 0x00000048;
limit |= (rend >> 8) & 0xffffff00;
- limit |= (link & 3) << 4;
+ limit |= (link_num & 3) << 4;
limit |= (nodeid & 7);
f1_write_config32(reg + 0x4, limit);
f1_write_config32(reg, base);
}
resource->flags |= IORESOURCE_STORED;
- sprintf(buf, " <node %d link %d>",
- nodeid, link);
+ sprintf(buf, " <node %x link %x>",
+ nodeid, link_num);
report_resource_stored(dev, resource, buf);
}
static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
{
struct resource *resource;
- unsigned link;
+ struct bus *link;
/* find out which link the VGA card is connected,
* we only deal with the 'first' vga card */
- for (link = 0; link < dev->links; link++) {
- if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
+ for (link = dev->link_list; link; link = link->next) {
+ if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
#if CONFIG_CONSOLE_VGA_MULTI == 1
- printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d dev->link[link] bus range [%d,%d]\n", vga_pri->bus->secondary,
- dev->link[link].secondary,dev->link[link].subordinate);
+ printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary,
+ link->secondary,link->subordinate);
/* We need to make sure the vga_pri is under the link */
- if((vga_pri->bus->secondary >= dev->link[link].secondary ) &&
- (vga_pri->bus->secondary <= dev->link[link].subordinate )
+ if((vga_pri->bus->secondary >= link->secondary ) &&
+ (vga_pri->bus->secondary <= link->subordinate )
)
#endif
break;
}
/* no VGA card installed */
- if (link == dev->links)
+ if (link == NULL)
return;
- printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link);
+ printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num);
/* allocate a temp resource for the legacy VGA buffer */
- resource = new_resource(dev, IOINDEX(4, link));
+ resource = new_resource(dev, IOINDEX(4, link->link_num));
if(!resource){
printk(BIOS_DEBUG, "VGA: %s out of resources.\n", dev_path(dev));
return;
static void amdk8_set_resources(device_t dev)
{
- unsigned nodeid, link;
- int i;
+ unsigned nodeid;
+ struct bus *bus;
+ struct resource *res;
/* Find the nodeid */
nodeid = amdk8_nodeid(dev);
/* Set each resource we have found */
- for(i = 0; i < dev->resources; i++) {
- struct resource *res = &dev->resource[i];
+ for(res = dev->resource_list; res; res = res->next) {
struct resource *old = NULL;
unsigned index;
compact_resources(dev);
- for(link = 0; link < dev->links; link++) {
- struct bus *bus;
- bus = &dev->link[link];
+ for(bus = dev->link_list; bus; bus = bus->next) {
if (bus->children) {
assign_resources(bus);
}
}
}
-static void amdk8_enable_resources(device_t dev)
-{
- pci_dev_enable_resources(dev);
- enable_childrens_resources(dev);
-}
-
static void mcf0_control_init(struct device *dev)
{
#if 0
}
static struct device_operations northbridge_operations = {
- .read_resources = amdk8_read_resources,
- .set_resources = amdk8_set_resources,
- .enable_resources = amdk8_enable_resources,
- .init = mcf0_control_init,
- .scan_bus = amdk8_scan_chains,
- .enable = 0,
- .ops_pci = 0,
+ .read_resources = amdk8_read_resources,
+ .set_resources = amdk8_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = mcf0_control_init,
+ .scan_bus = amdk8_scan_chains,
+ .enable = 0,
+ .ops_pci = 0,
};
static const struct pci_driver mcf0_driver __pci_driver = {
- .ops = &northbridge_operations,
+ .ops = &northbridge_operations,
.vendor = PCI_VENDOR_ID_AMD,
.device = 0x1100,
};
/* Find the already assigned resource pairs */
get_fx_devs();
for(reg = 0x80; reg <= 0xd8; reg+= 0x08) {
- uint32_t base, limit;
+ u32 base, limit;
base = f1_read_config32(reg);
limit = f1_read_config32(reg + 0x04);
/* Is this register allocated? */
if ((base & 3) != 0) {
- unsigned nodeid, link;
+ unsigned nodeid, reg_link;
device_t reg_dev;
nodeid = limit & 7;
- link = (limit >> 4) & 3;
+ reg_link = (limit >> 4) & 3;
reg_dev = __f0_dev[nodeid];
if (reg_dev) {
/* Reserve the resource */
struct resource *res;
- res = new_resource(reg_dev, IOINDEX(0x100 + reg, link));
+ res = new_resource(reg_dev, IOINDEX(0x100 + reg, reg_link));
if (res) {
res->base = base;
res->limit = limit;
#endif
}
-static void ram_resource(device_t dev, unsigned long index,
- unsigned long basek, unsigned long sizek)
-{
- struct resource *resource;
-
- if (!sizek) {
- return;
- }
- resource = new_resource(dev, index);
- resource->base = ((resource_t)basek) << 10;
- resource->size = ((resource_t)sizek) << 10;
- resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-}
-
-static void tolm_test(void *gp, struct device *dev, struct resource *new)
+static void my_tolm_test(void *gp, struct device *dev, struct resource *new)
{
struct resource **best_p = gp;
struct resource *best;
*best_p = best;
}
-static uint32_t find_pci_tolm(struct bus *bus)
+static u32 my_find_pci_tolm(struct bus *bus)
{
struct resource *min;
- uint32_t tolm;
+ u32 tolm;
min = 0;
- search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
+ search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, my_tolm_test, &min);
tolm = 0xffffffffUL;
if (min && tolm > min->base) {
tolm = min->base;
mem_hole.node_id = -1;
for (i = 0; i < fx_devs; i++) {
- uint32_t base;
- uint32_t hole;
+ u32 base;
+ u32 hole;
base = f1_read_config32(0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
//We need to double check if there is speical set on base reg and limit reg are not continous instead of hole, it will find out it's hole_startk
if(mem_hole.node_id==-1) {
- uint32_t limitk_pri = 0;
+ u32 limitk_pri = 0;
for(i=0; i<8; i++) {
- uint32_t base, limit;
+ u32 base, limit;
unsigned base_k, limit_k;
base = f1_read_config32(0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
limitk_pri = limit_k;
}
}
-
return mem_hole;
-
}
static void disable_hoist_memory(unsigned long hole_startk, int node_id)
{
int i;
device_t dev;
- uint32_t base, limit;
- uint32_t hoist;
- uint32_t hole_sizek;
+ u32 base, limit;
+ u32 hoist;
+ u32 hole_sizek;
//1. find which node has hole
return;
}
hoist = pci_read_config32(dev, 0xf0);
- if(hoist & 1)
+ if(hoist & 1) {
pci_write_config32(dev, 0xf0, 0);
- else {
+ } else {
base = pci_read_config32(dev, 0x40 + (node_id << 3));
f1_write_config32(0x40 + (node_id << 3),base - (hole_sizek << 2));
}
}
-static uint32_t hoist_memory(unsigned long hole_startk, int node_id)
+static u32 hoist_memory(unsigned long hole_startk, int node_id)
{
int i;
- uint32_t carry_over;
+ u32 carry_over;
device_t dev;
- uint32_t base, limit;
- uint32_t basek;
- uint32_t hoist;
+ u32 base, limit;
+ u32 basek;
+ u32 hoist;
carry_over = (4*1024*1024) - hole_startk;
{
#if CONFIG_PCI_64BIT_PREF_MEM == 1
struct resource *io, *mem1, *mem2;
- struct resource *resource, *last;
+ struct resource *res;
#endif
unsigned long mmio_basek;
- uint32_t pci_tolm;
+ u32 pci_tolm;
int i, idx;
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info mem_hole;
- unsigned reset_memhole = 1;
+ u32 reset_memhole = 1;
#endif
#if 0
mem2->base, mem2->limit, mem2->size, mem2->align);
#endif
- last = &dev->resource[dev->resources];
- for(resource = &dev->resource[0]; resource < last; resource++)
+ for(res = dev->resource_list; res; res = res->next)
{
- resource->flags |= IORESOURCE_ASSIGNED;
- resource->flags |= IORESOURCE_STORED;
- report_resource_stored(dev, resource, "");
-
+ res->flags |= IORESOURCE_ASSIGNED;
+ res->flags |= IORESOURCE_STORED;
+ report_resource_stored(dev, res, "");
}
#endif
- pci_tolm = find_pci_tolm(&dev->link[0]);
+ pci_tolm = my_find_pci_tolm(dev->link_list);
// FIXME handle interleaved nodes. If you fix this here, please fix
// amdfam10, too.
#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1
//We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
- uint32_t basek_pri;
+ u32 basek_pri;
for (i = 0; i < fx_devs; i++) {
- uint32_t base;
- uint32_t basek;
+ u32 base;
+ u32 basek;
base = f1_read_config32(0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
idx = 0x10;
for(i = 0; i < fx_devs; i++) {
- uint32_t base, limit;
- unsigned basek, limitk, sizek;
+ u32 base, limit;
+ u32 basek, limitk, sizek;
base = f1_read_config32(0x40 + (i << 3));
limit = f1_read_config32(0x44 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
idx += 0x10;
sizek -= pre_sizek;
#if CONFIG_WRITE_HIGH_TABLES==1
- if (i==0 && high_tables_base==0) {
+ if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA == 1
high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
#if CONFIG_WRITE_HIGH_TABLES==1
printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
i, mmio_basek, basek, limitk);
- if (i==0 && high_tables_base==0) {
+ if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
#if CONFIG_GFXUMA == 1
high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024);
}
#endif
}
- assign_resources(&dev->link[0]);
+ assign_resources(dev->link_list);
}
-static unsigned int amdk8_domain_scan_bus(device_t dev, unsigned int max)
+static u32 amdk8_domain_scan_bus(device_t dev, u32 max)
{
- unsigned reg;
+ u32 reg;
int i;
/* Unmap all of the HT chains */
for(reg = 0xe0; reg <= 0xec; reg += 4) {
f1_write_config32(reg, 0);
}
- max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0x18, 0), 0xff, max);
+ max = pci_scan_bus(dev->link_list, PCI_DEVFN(0x18, 0), 0xff, max);
/* Tune the hypertransport transaction for best performance.
* Including enabling relaxed ordering if it is safe.
device_t f0_dev;
f0_dev = __f0_dev[i];
if (f0_dev && f0_dev->enabled) {
- uint32_t httc;
+ u32 httc;
httc = pci_read_config32(f0_dev, HT_TRANSACTION_CONTROL);
httc &= ~HTTC_RSP_PASS_PW;
- if (!dev->link[0].disable_relaxed_ordering) {
+ if (!dev->link_list->disable_relaxed_ordering) {
httc |= HTTC_RSP_PASS_PW;
}
printk(BIOS_SPEW, "%s passpw: %s\n",
dev_path(dev),
- (!dev->link[0].disable_relaxed_ordering)?
+ (!dev->link_list->disable_relaxed_ordering)?
"enabled":"disabled");
pci_write_config32(f0_dev, HT_TRANSACTION_CONTROL, httc);
}
}
static struct device_operations pci_domain_ops = {
- .read_resources = amdk8_domain_read_resources,
- .set_resources = amdk8_domain_set_resources,
- .enable_resources = enable_childrens_resources,
- .init = 0,
- .scan_bus = amdk8_domain_scan_bus,
- .ops_pci_bus = &pci_cf8_conf1,
+ .read_resources = amdk8_domain_read_resources,
+ .set_resources = amdk8_domain_set_resources,
+ .enable_resources = NULL,
+ .init = NULL,
+ .scan_bus = amdk8_domain_scan_bus,
+ .ops_pci_bus = &pci_cf8_conf1,
};
-static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
+static void add_more_links(device_t dev, unsigned total_links)
+{
+ struct bus *link, *last = NULL;
+ int link_num;
+
+ for (link = dev->link_list; link; link = link->next)
+ last = link;
+
+ if (last) {
+ int links = total_links - last->link_num;
+ link_num = last->link_num;
+ if (links > 0) {
+ link = malloc(links*sizeof(*link));
+ if (!link)
+ die("Couldn't allocate more links!\n");
+ memset(link, 0, links*sizeof(*link));
+ last->next = link;
+ }
+ }
+ else {
+ link_num = -1;
+ link = malloc(total_links*sizeof(*link));
+ memset(link, 0, total_links*sizeof(*link));
+ dev->link_list = link;
+ }
+
+ for (link_num = link_num + 1; link_num < total_links; link_num++) {
+ link->link_num = link_num;
+ link->dev = dev;
+ link->next = link + 1;
+ last = link;
+ link = link->next;
+ }
+ last->next = NULL;
+}
+
+static u32 cpu_bus_scan(device_t dev, u32 max)
{
struct bus *cpu_bus;
device_t dev_mc;
get_option(&disable_siblings, "multi_core");
#endif
- // for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it still be 0)
- // How can I get the nb_cfg_54 of every node' nb_cfg_54 in bsp??? and differ d0 and e0 single core
-
+ // for pre_e0, nb_cfg_54 can not be set, (when you read it still is 0)
+ // How can I get the nb_cfg_54 of every node's nb_cfg_54 in bsp???
+ // and differ d0 and e0 single core
nb_cfg_54 = read_nb_cfg_54();
dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
}
/* Find which cpus are present */
- cpu_bus = &dev->link[0];
+ cpu_bus = dev->link_list;
for(i = 0; i < sysconf.nodes; i++) {
device_t cpu_dev, cpu;
struct device_path cpu_path;
*/
dev_f0 = dev_find_slot(0, PCI_DEVFN(0x18+i,0));
if(dev_f0) {
- dev_f0->links = 3;
- for(local_j=0;local_j<3;local_j++) {
- dev_f0->link[local_j].link = local_j;
- dev_f0->link[local_j].dev = dev_f0;
- }
+ add_more_links(dev_f0, 3);
}
-
}
e0_later_single_core = 0;
}
}
- unsigned jj;
+ u32 jj;
if(e0_later_single_core || disable_siblings) {
jj = 0;
} else
cpu->path.apic.apic_id += sysconf.apicid_offset;
} else
{
- if (cpu->path.apic.apic_id != 0)
- cpu->path.apic.apic_id += sysconf.apicid_offset;
+ if (cpu->path.apic.apic_id != 0)
+ cpu->path.apic.apic_id += sysconf.apicid_offset;
}
}
printk(BIOS_DEBUG, "CPU: %s %s\n",
static void cpu_bus_init(device_t dev)
{
- initialize_cpus(&dev->link[0]);
+ initialize_cpus(dev->link_list);
}
static void cpu_bus_noop(device_t dev)
}
static struct device_operations cpu_bus_ops = {
- .read_resources = cpu_bus_noop,
- .set_resources = cpu_bus_noop,
+ .read_resources = cpu_bus_noop,
+ .set_resources = cpu_bus_noop,
.enable_resources = cpu_bus_noop,
- .init = cpu_bus_init,
- .scan_bus = cpu_bus_scan,
+ .init = cpu_bus_init,
+ .scan_bus = cpu_bus_scan,
};
static void root_complex_enable_dev(struct device *dev)
projects / coreboot.git / blobdiff