missing file.

[coreboot.git] / src / northbridge / amd / amdk8 / misc_control.c

diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c
index 639e34fbaf0d2002bc5b8b817183c646a435c400..9d4e968267ee7bd021fb8dbad8aadea6d29006e1 100644 (file)
--- a/src/northbridge/amd/amdk8/misc_control.c
+++ b/src/northbridge/amd/amdk8/misc_control.c
@@ -8,6 +8,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
+#include "./cpu_rev.c"
 
 static void misc_control_init(struct device *dev)
 {
@@ -17,7 +18,60 @@ static void misc_control_init(struct device *dev)
        cmd = pci_read_config32(dev, 0x44);
        cmd |= (1<<6) | (1<<25);
        pci_write_config32(dev, 0x44, cmd );
+       if (is_cpu_pre_c0()) {
+               /* errata 58 */
+               cmd = pci_read_config32(dev, 0x80);
+               cmd &= ~(1<<0);
+               pci_write_config32(dev, 0x80, cmd );
+               cmd = pci_read_config32(dev, 0x84);
+               cmd &= ~(1<<24);
+               cmd &= ~(1<<8);
+               pci_write_config32(dev, 0x84, cmd );
+               /* errata 66 */
+               cmd = pci_read_config32(dev, 0x70);
+               cmd &= ~(1<<0);
+               cmd |= (1<<1);
+               pci_write_config32(dev, 0x70, cmd );
+               cmd = pci_read_config32(dev, 0x7c);
+               cmd &= ~(3<<4);
+               pci_write_config32(dev, 0x7c, cmd );
+       }
+       else {
+               /* errata 98 */
+#if 0          
+               cmd = pci_read_config32(dev, 0xd4);
+               if(cmd != 0x04e20707) {
+                       cmd = 0x04e20707;
+                       pci_write_config32(dev, 0xd4, cmd );
+                       hard_reset();
+               }
+#endif
 
+               cmd = 0x04e20707;
+               pci_write_config32(dev, 0xd4, cmd );
+       }
+
+/*
+ * FIXME: This preprocessor check is a mere workaround. 
+ * The right fix is to walk over all links on all nodes
+ * and set the FIFO read pointer optimization value to
+ * 0x25 for each link connected to an AMD HT device.
+ *
+ * The reason this is only enabled for machines with more 
+ * than one CPU is that Athlon64 machines don't have the
+ * link at all that is optimized in the code.
+ */
+
+#if CONFIG_MAX_CPUS > 1        
+       cmd = pci_read_config32(dev, 0xdc);
+       if((cmd & 0x0000ff00) != 0x02500) {
+               cmd &= 0xffff00ff;
+               cmd |= 0x00002500;
+               pci_write_config32(dev, 0xdc, cmd );
+               printk_debug("resetting cpu\n");
+               hard_reset();
+       }
+#endif 
        printk_debug("done.\n");
 }