printk_foo -> printk(BIOS_FOO, ...)

[coreboot.git] / src / northbridge / amd / amdk8 / misc_control.c

diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c
index c7176c3b0d7712e15c23c3ff190e42b73991183a..1b40eb1381b2eaf47cd4fe7e9756e6e30dcae25a 100644 (file)
--- a/src/northbridge/amd/amdk8/misc_control.c
+++ b/src/northbridge/amd/amdk8/misc_control.c
@@ -14,7 +14,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include <part/hard_reset.h>
+#include <reset.h>
 #include <pc80/mc146818rtc.h>
 #include <bitops.h>
 #include <cpu/amd/model_fxx_rev.h>
@@ -43,7 +43,7 @@ static void mcf3_read_resources(device_t dev)
        pci_dev_read_resources(dev);
 
        /* If we are not the first processor don't allocate the gart apeture */
-       if (dev->path.u.pci.devfn != PCI_DEVFN(0x18, 3)) {
+       if (dev->path.pci.devfn != PCI_DEVFN(0x18, 3)) {
                return;
        }
 
@@ -53,7 +53,7 @@ static void mcf3_read_resources(device_t dev)
        if (iommu) {
                /* Add a Gart apeture resource */
                resource = new_resource(dev, 0x94);
-               resource->size = iommu?AGP_APERTURE_SIZE:1;
+               resource->size = CONFIG_AGP_APERTURE_SIZE;
                resource->align = log2(resource->size);
                resource->gran  = log2(resource->size);
                resource->limit = 0xffffffff; /* 4G */
@@ -112,7 +112,7 @@ static void misc_control_init(struct device *dev)
        int needs_reset;
        struct device *f0_dev, *f2_dev;
        
-       printk_debug("NB: Function 3 Misc Control.. ");
+       printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. ");
        needs_reset = 0;
 
        /* Disable Machine checks from Invalid Locations.
@@ -121,6 +121,7 @@ static void misc_control_init(struct device *dev)
        cmd = pci_read_config32(dev, 0x44);
        cmd |= (1<<6) | (1<<25);
        pci_write_config32(dev, 0x44, cmd );
+#if CONFIG_K8_REV_F_SUPPORT == 0
        if (is_cpu_pre_c0()) {
 
                /* Errata 58
@@ -161,14 +162,14 @@ static void misc_control_init(struct device *dev)
        }
        else if(is_cpu_pre_d0()) {
                uint32_t dcl;
-               f2_dev = dev_find_slot(0, dev->path.u.pci.devfn - 3 + 2);
+               f2_dev = dev_find_slot(0, dev->path.pci.devfn - 3 + 2);
                /* Errata 98 
                 * Set Clk Ramp Hystersis to 7
                 * Clock Power/Timing Low
                 */
                cmd_ref = 0x04e20707; /* Registered */
                dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW);
-               if (dcl & DCL_UnBufDimm) {
+               if (dcl & DCL_UnBuffDimm) {
                        cmd_ref = 0x000D0701; /* Unbuffered */
                }
                cmd = pci_read_config32(dev, 0xd4);
@@ -177,8 +178,9 @@ static void misc_control_init(struct device *dev)
                        needs_reset = 1; /* Needed? */
                }
        }
+#endif
        /* Optimize the Link read pointers */
-       f0_dev = dev_find_slot(0, dev->path.u.pci.devfn - 3);
+       f0_dev = dev_find_slot(0, dev->path.pci.devfn - 3);
        if (f0_dev) {
                int link;
                cmd_ref = cmd = pci_read_config32(dev, 0xdc);
@@ -203,13 +205,13 @@ static void misc_control_init(struct device *dev)
                }
        }
        else {
-               printk_err("Missing f0 device!\n");
+               printk(BIOS_ERR, "Missing f0 device!\n");
        }
        if (needs_reset) {
-               printk_debug("resetting cpu\n");
+               printk(BIOS_DEBUG, "resetting cpu\n");
                hard_reset();
        }
-       printk_debug("done.\n");
+       printk(BIOS_DEBUG, "done.\n");
 }
 
 
@@ -222,7 +224,7 @@ static struct device_operations mcf3_ops  = {
        .ops_pci          = 0,
 };
 
-static struct pci_driver mcf3_driver __pci_driver = {
+static const struct pci_driver mcf3_driver __pci_driver = {
        .ops    = &mcf3_ops,
        .vendor = PCI_VENDOR_ID_AMD,
        .device = 0x1103,