#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include <part/hard_reset.h>
+#include <reset.h>
#include <pc80/mc146818rtc.h>
#include <bitops.h>
-#include "./cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
+
#include "amdk8.h"
/**
pci_dev_read_resources(dev);
/* If we are not the first processor don't allocate the gart apeture */
- if (dev->path.u.pci.devfn != PCI_DEVFN(0x18, 0x3)) {
+ if (dev->path.pci.devfn != PCI_DEVFN(0x18, 3)) {
return;
}
if (iommu) {
/* Add a Gart apeture resource */
resource = new_resource(dev, 0x94);
- resource->size = iommu?AGP_APERTURE_SIZE:1;
+ resource->size = CONFIG_AGP_APERTURE_SIZE;
resource->align = log2(resource->size);
resource->gran = log2(resource->size);
resource->limit = 0xffffffff; /* 4G */
if (resource) {
device_t pdev;
uint32_t gart_base, gart_acr;
+
/* Remember this resource has been stored */
resource->flags |= IORESOURCE_STORED;
- /*Find the size of the GART aperture */
- gart_acr = (0<<6)|(0<<5)|(0<<4)| ((log2(resource->size) - 25) << 1)|(0<<0);
+ /* Find the size of the GART aperture */
+ gart_acr = (0<<6)|(0<<5)|(0<<4)|((resource->gran - 25) << 1)|(0<<0);
/* Get the base address */
gart_base = ((resource->base) >> 25) & 0x00007fff;
/* Update the other northbriges */
pdev = 0;
- while (pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev)) {
- /* Store GART size but don't enable it */
+ while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) {
+ /* Store the GART size but don't enable it */
pci_write_config32(pdev, 0x90, gart_acr);
/* Store the GART base address */
int needs_reset;
struct device *f0_dev, *f2_dev;
- printk_debug("NB: Function 3 Misc Control.. ");
+ printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. ");
needs_reset = 0;
/* Disable Machine checks from Invalid Locations.
cmd = pci_read_config32(dev, 0x44);
cmd |= (1<<6) | (1<<25);
pci_write_config32(dev, 0x44, cmd );
+#if CONFIG_K8_REV_F_SUPPORT == 0
if (is_cpu_pre_c0()) {
/* Errata 58
needs_reset = 1; /* Needed? */
}
}
- else {
+ else if(is_cpu_pre_d0()) {
uint32_t dcl;
- f2_dev = dev_find_slot(0, dev->path.u.pci.devfn - 3 + 2);
+ f2_dev = dev_find_slot(0, dev->path.pci.devfn - 3 + 2);
/* Errata 98
* Set Clk Ramp Hystersis to 7
* Clock Power/Timing Low
*/
cmd_ref = 0x04e20707; /* Registered */
dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW);
- if (dcl & DCL_UnBufDimm) {
+ if (dcl & DCL_UnBuffDimm) {
cmd_ref = 0x000D0701; /* Unbuffered */
}
cmd = pci_read_config32(dev, 0xd4);
needs_reset = 1; /* Needed? */
}
}
-#if CONFIG_MAX_CPUS > 1
-/* Single CPU systems don't seem to need this. It might cause resets? (YhLu) */
+#endif
/* Optimize the Link read pointers */
- f0_dev = dev_find_slot(0, dev->path.u.pci.devfn - 3);
+ f0_dev = dev_find_slot(0, dev->path.pci.devfn - 3);
if (f0_dev) {
int link;
cmd_ref = cmd = pci_read_config32(dev, 0xdc);
/* This works on an Athlon64 because unimplemented links return 0 */
reg = 0x98 + (link * 0x20);
link_type = pci_read_config32(f0_dev, reg);
- if (link_type & LinkConnected) {
- cmd &= 0xff << (link *8);
+ /* Only handle coherent link here please */
+ if ((link_type & (LinkConnected|InitComplete|NonCoherent))
+ == (LinkConnected|InitComplete))
+ {
+ cmd &= ~(0xff << (link *8));
/* FIXME this assumes the device on the other side is an AMD device */
cmd |= 0x25 << (link *8);
}
}
}
else {
- printk_err("Missing f0 device!\n");
+ printk(BIOS_ERR, "Missing f0 device!\n");
}
-#endif
if (needs_reset) {
- printk_debug("resetting cpu\n");
+ printk(BIOS_DEBUG, "resetting cpu\n");
hard_reset();
}
- printk_debug("done.\n");
+ printk(BIOS_DEBUG, "done.\n");
}
.enable_resources = pci_dev_enable_resources,
.init = misc_control_init,
.scan_bus = 0,
+ .ops_pci = 0,
};
-static struct pci_driver mcf3_driver __pci_driver = {
+static const struct pci_driver mcf3_driver __pci_driver = {
.ops = &mcf3_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = 0x1103,