#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <part/hard_reset.h>
-#include "./cpu_rev.c"
+#include <pc80/mc146818rtc.h>
+#include <bitops.h>
+#include <cpu/amd/model_fxx_rev.h>
+
#include "amdk8.h"
+/**
+ * @brief Read resources for AGP aperture
+ *
+ * @param
+ *
+ * There is only one AGP aperture resource needed. The resoruce is added to
+ * the northbridge of BSP.
+ *
+ * The same trick can be used to augment legacy VGA resources which can
+ * be detect by generic pci reousrce allocator for VGA devices.
+ * BAD: it is more tricky than I think, the resource allocation code is
+ * implemented in a way to NOT DOING legacy VGA resource allcation on
+ * purpose :-(.
+ */
static void mcf3_read_resources(device_t dev)
{
struct resource *resource;
-
+ unsigned char iommu;
/* Read the generic PCI resources */
pci_dev_read_resources(dev);
/* If we are not the first processor don't allocate the gart apeture */
- if (dev->path.u.pci.devfn != PCI_DEVFN(0x18, 0x3)) {
+ if (dev->path.pci.devfn != PCI_DEVFN(0x18, 3)) {
return;
}
-
- /* Add a 64M Gart apeture resource */
- if (dev->resources < MAX_RESOURCES) {
- resource = &dev->resource[dev->resources];
- dev->resources++;
- resource->base = 0;
- resource->size = AGP_APERTURE_SIZE;
+
+ iommu = 1;
+ get_option(&iommu, "iommu");
+
+ if (iommu) {
+ /* Add a Gart apeture resource */
+ resource = new_resource(dev, 0x94);
+ resource->size = iommu?AGP_APERTURE_SIZE:1;
resource->align = log2(resource->size);
resource->gran = log2(resource->size);
resource->limit = 0xffffffff; /* 4G */
resource->flags = IORESOURCE_MEM;
- resource->index = 0x94;
- } else {
- printk_err("%s Unexpeted resource shortage\n", dev_path(dev));
}
}
-static void mcf3_set_resources(device_t dev)
+static void set_agp_aperture(device_t dev)
{
- struct resource *resource, *last;
- last = &dev->resource[dev->resources];
- for (resource = &dev->resource[0]; resource < last; resource++) {
- if (resource->index == 0x94) {
- device_t pdev;
- uint32_t base;
- uint32_t size;
+ struct resource *resource;
+
+ resource = probe_resource(dev, 0x94);
+ if (resource) {
+ device_t pdev;
+ uint32_t gart_base, gart_acr;
+
+ /* Remember this resource has been stored */
+ resource->flags |= IORESOURCE_STORED;
+
+ /* Find the size of the GART aperture */
+ gart_acr = (0<<6)|(0<<5)|(0<<4)|((resource->gran - 25) << 1)|(0<<0);
+
+ /* Get the base address */
+ gart_base = ((resource->base) >> 25) & 0x00007fff;
+
+ /* Update the other northbriges */
+ pdev = 0;
+ while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) {
+ /* Store the GART size but don't enable it */
+ pci_write_config32(pdev, 0x90, gart_acr);
+
+ /* Store the GART base address */
+ pci_write_config32(pdev, 0x94, gart_base);
+
+ /* Don't set the GART Table base address */
+ pci_write_config32(pdev, 0x98, 0);
- size = (0<<6)|(0<<5)|(0<<4)|
- ((log2(resource->size) - 25) << 1)|(0<<0);
- base = ((resource->base) >> 25) & 0x00007fff;
- pdev = 0;
- while (pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev)) {
- /* I want a 64M GART apeture */
- pci_write_config32(pdev, 0x90, (0<<6)|(0<<5)|(0<<4)|(1<<1)|(0<<0));
- /* Store the GART base address */
- pci_write_config32(pdev, 0x94, base);
- /* Don't set the GART Table base address */
- pci_write_config32(pdev, 0x98, 0);
-
- printk_debug("%s %02x <- [0x%08lx - 0x%08lx] mem <gart>\n",
- dev_path(pdev), resource->index, resource->base,
- resource->base + resource->size - 1);
- }
- /* Remember this resource has been stored */
- resource->flags |= IORESOURCE_STORED;
+ /* Report the resource has been stored... */
+ report_resource_stored(pdev, resource, " <gart>");
}
}
+}
+
+static void mcf3_set_resources(device_t dev)
+{
+ /* Set the gart apeture */
+ set_agp_aperture(dev);
+
/* Set the generic PCI resources */
pci_dev_set_resources(dev);
}
cmd = pci_read_config32(dev, 0x44);
cmd |= (1<<6) | (1<<25);
pci_write_config32(dev, 0x44, cmd );
+#if K8_REV_F_SUPPORT == 0
if (is_cpu_pre_c0()) {
/* Errata 58
needs_reset = 1; /* Needed? */
}
}
- else {
+ else if(is_cpu_pre_d0()) {
uint32_t dcl;
- f2_dev = dev_find_slot(0, dev->path.u.pci.devfn - 3 + 2);
+ f2_dev = dev_find_slot(0, dev->path.pci.devfn - 3 + 2);
/* Errata 98
* Set Clk Ramp Hystersis to 7
* Clock Power/Timing Low
needs_reset = 1; /* Needed? */
}
}
-#if CONFIG_MAX_CPUS > 1
-/* Single CPU systems don't seem to need this. It might cause resets? (YhLu) */
+#endif
/* Optimize the Link read pointers */
- f0_dev = dev_find_slot(0, dev->path.u.pci.devfn - 3);
+ f0_dev = dev_find_slot(0, dev->path.pci.devfn - 3);
if (f0_dev) {
int link;
cmd_ref = cmd = pci_read_config32(dev, 0xdc);
/* This works on an Athlon64 because unimplemented links return 0 */
reg = 0x98 + (link * 0x20);
link_type = pci_read_config32(f0_dev, reg);
- if (link_type & LinkConnected) {
- cmd &= 0xff << (link *8);
+ /* Only handle coherent link here please */
+ if ((link_type & (LinkConnected|InitComplete|NonCoherent))
+ == (LinkConnected|InitComplete))
+ {
+ cmd &= ~(0xff << (link *8));
/* FIXME this assumes the device on the other side is an AMD device */
cmd |= 0x25 << (link *8);
}
else {
printk_err("Missing f0 device!\n");
}
-#endif
if (needs_reset) {
printk_debug("resetting cpu\n");
hard_reset();
.enable_resources = pci_dev_enable_resources,
.init = misc_control_init,
.scan_bus = 0,
+ .ops_pci = 0,
};
-static struct pci_driver mcf3_driver __pci_driver = {
+static const struct pci_driver mcf3_driver __pci_driver = {
.ops = &mcf3_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = 0x1103,
projects / coreboot.git / blobdiff