Revert "CMOS: Add set_option and rework get_option."

[coreboot.git] / src / northbridge / amd / amdk8 / misc_control.c

diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c
index 4938c453d77d5c1398fe04ca3c74338abb5be76b..03758c63bacf541607640375132b4207d1f94e97 100644 (file)
--- a/src/northbridge/amd/amdk8/misc_control.c
+++ b/src/northbridge/amd/amdk8/misc_control.c
@@ -17,7 +17,8 @@
 #include <part/hard_reset.h>
 #include <pc80/mc146818rtc.h>
 #include <bitops.h>
-#include "./cpu_rev.c"
+#include <cpu/amd/model_fxx_rev.h>
+
 #include "amdk8.h"
 
 /**
@@ -42,7 +43,7 @@ static void mcf3_read_resources(device_t dev)
        pci_dev_read_resources(dev);
 
        /* If we are not the first processor don't allocate the gart apeture */
-       if (dev->path.u.pci.devfn != PCI_DEVFN(0x18, 0x3)) {
+       if (dev->path.pci.devfn != PCI_DEVFN(0x18, 3)) {
                return;
        }
 
@@ -68,19 +69,20 @@ static void set_agp_aperture(device_t dev)
        if (resource) {
                device_t pdev;
                uint32_t gart_base, gart_acr;
+
                /* Remember this resource has been stored */
                resource->flags |= IORESOURCE_STORED;
 
-               /*Find the size of the GART aperture */
-               gart_acr  = (0<<6)|(0<<5)|(0<<4)| ((log2(resource->size) - 25) << 1)|(0<<0);
+               /* Find the size of the GART aperture */
+               gart_acr = (0<<6)|(0<<5)|(0<<4)|((resource->gran - 25) << 1)|(0<<0);
 
                /* Get the base address */
                gart_base = ((resource->base) >> 25) & 0x00007fff;
                
                /* Update the other northbriges */
                pdev = 0;
-               while (pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev)) {
-                       /* Store GART size but don't enable it */
+               while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) {
+                       /* Store the GART size but don't enable it */
                        pci_write_config32(pdev, 0x90, gart_acr);
 
                        /* Store the GART base address */
@@ -119,6 +121,7 @@ static void misc_control_init(struct device *dev)
        cmd = pci_read_config32(dev, 0x44);
        cmd |= (1<<6) | (1<<25);
        pci_write_config32(dev, 0x44, cmd );
+#if K8_REV_F_SUPPORT == 0
        if (is_cpu_pre_c0()) {
 
                /* Errata 58
@@ -157,9 +160,9 @@ static void misc_control_init(struct device *dev)
                        needs_reset = 1; /* Needed? */
                }
        }
-       else {
+       else if(is_cpu_pre_d0()) {
                uint32_t dcl;
-               f2_dev = dev_find_slot(0, dev->path.u.pci.devfn - 3 + 2);
+               f2_dev = dev_find_slot(0, dev->path.pci.devfn - 3 + 2);
                /* Errata 98 
                 * Set Clk Ramp Hystersis to 7
                 * Clock Power/Timing Low
@@ -175,10 +178,9 @@ static void misc_control_init(struct device *dev)
                        needs_reset = 1; /* Needed? */
                }
        }
-#if CONFIG_MAX_CPUS > 1 
-/* Single CPU systems don't seem to need this. It might cause resets? (YhLu) */
+#endif
        /* Optimize the Link read pointers */
-       f0_dev = dev_find_slot(0, dev->path.u.pci.devfn - 3);
+       f0_dev = dev_find_slot(0, dev->path.pci.devfn - 3);
        if (f0_dev) {
                int link;
                cmd_ref = cmd = pci_read_config32(dev, 0xdc);
@@ -188,8 +190,11 @@ static void misc_control_init(struct device *dev)
                        /* This works on an Athlon64 because unimplemented links return 0 */
                        reg = 0x98 + (link * 0x20);
                        link_type = pci_read_config32(f0_dev, reg);
-                       if (link_type & LinkConnected) {
-                               cmd &= 0xff << (link *8);
+                       /* Only handle coherent link here please */
+                       if ((link_type & (LinkConnected|InitComplete|NonCoherent)) 
+                               == (LinkConnected|InitComplete))
+                       {
+                               cmd &= ~(0xff << (link *8));
                                /* FIXME this assumes the device on the other side is an AMD device */
                                cmd |= 0x25 << (link *8);
                        }
@@ -202,7 +207,6 @@ static void misc_control_init(struct device *dev)
        else {
                printk_err("Missing f0 device!\n");
        }
-#endif 
        if (needs_reset) {
                printk_debug("resetting cpu\n");
                hard_reset();
@@ -217,9 +221,10 @@ static struct device_operations mcf3_ops  = {
        .enable_resources = pci_dev_enable_resources,
        .init             = misc_control_init,
        .scan_bus         = 0,
+       .ops_pci          = 0,
 };
 
-static struct pci_driver mcf3_driver __pci_driver = {
+static const struct pci_driver mcf3_driver __pci_driver = {
        .ops    = &mcf3_ops,
        .vendor = PCI_VENDOR_ID_AMD,
        .device = 0x1103,