#include <device/pci_ids.h>
#include <device/hypertransport_def.h>
-#ifndef CONFIG_K8_HT_FREQ_1G_SUPPORT
- #define CONFIG_K8_HT_FREQ_1G_SUPPORT 0
-#endif
-
-#ifndef RAMINIT_SYSINFO
- #define RAMINIT_SYSINFO 0
-#endif
-
-#ifndef K8_ALLOCATE_IO_RANGE
- #define K8_ALLOCATE_IO_RANGE 0
-#endif
-
// Do we need allocate MMIO? Current We direct last 64M to sblink only, We can not lose access to last 4M range to ROM
#ifndef K8_ALLOCATE_MMIO_RANGE
#define K8_ALLOCATE_MMIO_RANGE 0
}
printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\n", pos, freq_cap);
- //printk(BIOS_SPEW, "capping to 800/600/400/200 MHz\n");
- //freq_cap &= 0x3f;
+
+ #if CONFIG_SOUTHBRIDGE_VIA_K8M890 == 1
+ freq_cap &= 0x3f;
+ printk(BIOS_INFO, "Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed.\n");
+ #endif
return freq_cap;
}
return needs_reset;
}
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid, struct sys_info *sysinfo)
#else
static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid)
uint8_t next_unitid, last_unitid;
unsigned uoffs;
-#if RAMINIT_SYSINFO == 0
+#if !CONFIG_RAMINIT_SYSINFO
int reset_needed = 0;
#endif
flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
offs = ((flags>>10) & 1) ? PCI_HT_SLAVE1_OFFS : PCI_HT_SLAVE0_OFFS;
- #if RAMINIT_SYSINFO == 1
+ #if CONFIG_RAMINIT_SYSINFO
/* store the link pair here and we will Setup the Hypertransport link later, after we get final FID/VID */
{
struct link_pair_st *link_pair = &sysinfo->link_pair[sysinfo->link_pair_num];
flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f;
pci_write_config16(PCI_DEV(bus, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags);
- #if RAMINIT_SYSINFO == 1
+ #if CONFIG_RAMINIT_SYSINFO
// Here need to change the dev in the array
int i;
for(i=0;i<sysinfo->link_pair_num;i++)
}
#endif
-#if RAMINIT_SYSINFO == 0
+#if !CONFIG_RAMINIT_SYSINFO
return reset_needed;
#endif
}
#if 0
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
static void ht_setup_chain(device_t udev, unsigned upos, struct sys_info *sysinfo)
#else
static int ht_setup_chain(device_t udev, unsigned upos)
offset_unitid = 1;
#endif
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
ht_setup_chainx(udev, upos, 0, offset_unitid, sysinfo);
#else
return ht_setup_chainx(udev, upos, 0, offset_unitid);
return reset_needed;
}
-#if defined(CONFIG_SOUTHBRIDGE_NVIDIA_CK804) // || defined(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55)
+#if CONFIG_SOUTHBRIDGE_NVIDIA_CK804 // || CONFIG_SOUTHBRIDGE_NVIDIA_MCP55
static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val)
{
uint32_t dword;
}
#endif
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
static void ht_setup_chains(uint8_t ht_c_num, struct sys_info *sysinfo)
#else
static int ht_setup_chains(uint8_t ht_c_num)
device_t udev;
uint8_t i;
-#if RAMINIT_SYSINFO == 0
+#if !CONFIG_RAMINIT_SYSINFO
int reset_needed = 0;
#else
sysinfo->link_pair_num = 0;
upos = ((reg & 0xf00)>>8) * 0x20 + 0x80;
udev = PCI_DEV(0, devpos, 0);
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
ht_setup_chainx(udev,upos,busn, offset_unitid, sysinfo); // all not
#else
reset_needed |= ht_setup_chainx(udev,upos,busn, offset_unitid); //all not
}
-#if RAMINIT_SYSINFO == 0
+#if !CONFIG_RAMINIT_SYSINFO
reset_needed |= optimize_link_read_pointers_chain(ht_c_num);
return reset_needed;
static inline unsigned get_nodes(void);
#endif
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
static void ht_setup_chains_x(struct sys_info *sysinfo)
#else
static int ht_setup_chains_x(void)
uint8_t next_busn;
uint8_t ht_c_num;
uint8_t nodes;
-#if K8_ALLOCATE_IO_RANGE == 1
+#if CONFIG_K8_ALLOCATE_IO_RANGE
unsigned next_io_base;
#endif
reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
/* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn=0x3f+1 */
print_linkn_in("SBLink=", ((reg>>8) & 3) );
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
sysinfo->sblk = (reg>>8) & 3;
sysinfo->sbbusn = 0;
sysinfo->nodes = nodes;
next_busn=0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/
-#if K8_ALLOCATE_IO_RANGE == 1
+#if CONFIG_K8_ALLOCATE_IO_RANGE
/* io range allocation */
tempreg = 0 | (((reg>>8) & 0x3) << 4 )| (0x3<<12); //limit
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4, tempreg);
for(ht_c_num=1;ht_c_num<4; ht_c_num++) {
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0);
-#if K8_ALLOCATE_IO_RANGE == 1
+#if CONFIG_K8_ALLOCATE_IO_RANGE
/* io range allocation */
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc4 + ht_c_num * 8, 0);
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc0 + ht_c_num * 8, 0);
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, tempreg);
next_busn+=0x3f+1;
-#if K8_ALLOCATE_IO_RANGE == 1
+#if CONFIG_K8_ALLOCATE_IO_RANGE
/* io range allocation */
tempreg = nodeid | (linkn<<4) | ((next_io_base+0x3)<<12); //limit
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg);
pci_write_config32(dev, regpos, reg);
}
-#if K8_ALLOCATE_IO_RANGE == 1
+#if CONFIG_K8_ALLOCATE_IO_RANGE
/* io range allocation */
for(i = 0; i< 4; i++) {
unsigned regpos;
}
}
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
sysinfo->ht_c_num = i;
ht_setup_chains(i, sysinfo);
sysinfo->sbdn = get_sbdn(sysinfo->sbbusn);
}
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
static int optimize_link_incoherent_ht(struct sys_info *sysinfo)
{
// We need to use recorded link pair info to optimize the link