Improve VIA K8M890 HT settings. Use recommended settings for ROMSIP and

[coreboot.git] / src / northbridge / amd / amdk8 / incoherent_ht.c

diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index 6a8551621149fda1b05675fd3cd36f3bdf0bd48b..4d0d0259f65326498b8f7790b6e73e6562b18d22 100644 (file)
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -7,18 +7,6 @@
 #include <device/pci_ids.h>
 #include <device/hypertransport_def.h>
 
-#ifndef CONFIG_K8_HT_FREQ_1G_SUPPORT
-       #define CONFIG_K8_HT_FREQ_1G_SUPPORT 0
-#endif
-
-#ifndef RAMINIT_SYSINFO
-       #define RAMINIT_SYSINFO 0
-#endif
-
-#ifndef K8_ALLOCATE_IO_RANGE
-       #define K8_ALLOCATE_IO_RANGE 0
-#endif
-
 // Do we need allocate MMIO? Current We direct last 64M to sblink only, We can not lose access to last 4M range to ROM
 #ifndef K8_ALLOCATE_MMIO_RANGE
        #define K8_ALLOCATE_MMIO_RANGE 0
@@ -67,10 +55,12 @@ static uint8_t ht_lookup_slave_capability(device_t dev)
        return ht_lookup_capability(dev, 0); // Slave/Primary Interface Block Format
 }
 
+#if 0
 static uint8_t ht_lookup_host_capability(device_t dev)
 {
        return ht_lookup_capability(dev, 1); // Host/Secondary Interface Block Format
 }
+#endif
 
 static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid)
 {
@@ -158,8 +148,11 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos)
        }
 
        printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\n", pos, freq_cap);
-       //printk(BIOS_SPEW, "capping to 800/600/400/200 MHz\n");
-       //freq_cap &= 0x3f;
+
+       #if CONFIG_SOUTHBRIDGE_VIA_K8M890 == 1
+       freq_cap &= 0x3f;
+       printk(BIOS_INFO, "Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed.\n");
+       #endif
        return freq_cap;
 }
 
@@ -295,7 +288,7 @@ static int ht_optimize_link(
        return needs_reset;
 }
 
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
 static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid, struct sys_info *sysinfo)
 #else
 static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid)
@@ -306,7 +299,7 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of
        uint8_t next_unitid, last_unitid;
        unsigned uoffs;
 
-#if RAMINIT_SYSINFO == 0
+#if !CONFIG_RAMINIT_SYSINFO
        int reset_needed = 0;
 #endif
 
@@ -413,7 +406,7 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of
                flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
                offs = ((flags>>10) & 1) ? PCI_HT_SLAVE1_OFFS : PCI_HT_SLAVE0_OFFS;
 
-               #if RAMINIT_SYSINFO == 1
+               #if CONFIG_RAMINIT_SYSINFO
                /* store the link pair here and we will Setup the Hypertransport link later, after we get final FID/VID */
                {
                        struct link_pair_st *link_pair = &sysinfo->link_pair[sysinfo->link_pair_num];
@@ -444,14 +437,14 @@ end_of_chain: ;
 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
        if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used ) {
                uint16_t flags;
-               int i;
                flags = pci_read_config16(PCI_DEV(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
                flags &= ~0x1f;
                flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f;
                pci_write_config16(PCI_DEV(bus, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags);
 
-               #if RAMINIT_SYSINFO == 1
+               #if CONFIG_RAMINIT_SYSINFO
                // Here need to change the dev in the array
+               int i;
                for(i=0;i<sysinfo->link_pair_num;i++)
                {
                        struct link_pair_st *link_pair = &sysinfo->link_pair[i];
@@ -468,13 +461,14 @@ end_of_chain: ;
        }
 #endif
 
-#if RAMINIT_SYSINFO == 0
+#if !CONFIG_RAMINIT_SYSINFO
        return reset_needed;
 #endif
 
 }
 
-#if RAMINIT_SYSINFO == 1
+#if 0
+#if CONFIG_RAMINIT_SYSINFO
 static void ht_setup_chain(device_t udev, unsigned upos, struct sys_info *sysinfo)
 #else
 static int ht_setup_chain(device_t udev, unsigned upos)
@@ -498,12 +492,14 @@ static int ht_setup_chain(device_t udev, unsigned upos)
        offset_unitid = 1;
 #endif
 
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
        ht_setup_chainx(udev, upos, 0, offset_unitid, sysinfo);
 #else
        return ht_setup_chainx(udev, upos, 0, offset_unitid);
 #endif
 }
+#endif
+
 static int optimize_link_read_pointer(uint8_t node, uint8_t linkn, uint8_t linkt, uint8_t val)
 {
        uint32_t dword, dword_old;
@@ -571,6 +567,7 @@ static int optimize_link_read_pointers_chain(uint8_t ht_c_num)
        return reset_needed;
 }
 
+#if CONFIG_SOUTHBRIDGE_NVIDIA_CK804 // || CONFIG_SOUTHBRIDGE_NVIDIA_MCP55
 static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val)
 {
        uint32_t dword;
@@ -596,6 +593,7 @@ static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt,
 
        return 0;
 }
+
 static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid,  unsigned val)
 {
        int reset_needed;
@@ -627,9 +625,9 @@ static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid,
 
        return reset_needed;
 }
+#endif
 
-
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
 static void ht_setup_chains(uint8_t ht_c_num, struct sys_info *sysinfo)
 #else
 static int ht_setup_chains(uint8_t ht_c_num)
@@ -644,7 +642,7 @@ static int ht_setup_chains(uint8_t ht_c_num)
        device_t udev;
        uint8_t i;
 
-#if RAMINIT_SYSINFO == 0
+#if !CONFIG_RAMINIT_SYSINFO
        int reset_needed = 0;
 #else
        sysinfo->link_pair_num = 0;
@@ -685,7 +683,7 @@ static int ht_setup_chains(uint8_t ht_c_num)
                upos = ((reg & 0xf00)>>8) * 0x20 + 0x80;
                udev =  PCI_DEV(0, devpos, 0);
 
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
                ht_setup_chainx(udev,upos,busn, offset_unitid, sysinfo); // all not
 #else
                reset_needed |= ht_setup_chainx(udev,upos,busn, offset_unitid); //all not
@@ -693,7 +691,7 @@ static int ht_setup_chains(uint8_t ht_c_num)
 
        }
 
-#if RAMINIT_SYSINFO == 0
+#if !CONFIG_RAMINIT_SYSINFO
        reset_needed |= optimize_link_read_pointers_chain(ht_c_num);
 
        return reset_needed;
@@ -705,7 +703,7 @@ static int ht_setup_chains(uint8_t ht_c_num)
 static inline unsigned get_nodes(void);
 #endif
 
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
 static void ht_setup_chains_x(struct sys_info *sysinfo)
 #else
 static int ht_setup_chains_x(void)
@@ -717,7 +715,7 @@ static int ht_setup_chains_x(void)
        uint8_t next_busn;
        uint8_t ht_c_num;
        uint8_t nodes;
-#if K8_ALLOCATE_IO_RANGE == 1
+#if CONFIG_K8_ALLOCATE_IO_RANGE
        unsigned next_io_base;
 #endif
 
@@ -727,7 +725,7 @@ static int ht_setup_chains_x(void)
        reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
        /* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn=0x3f+1 */
        print_linkn_in("SBLink=", ((reg>>8) & 3) );
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
        sysinfo->sblk = (reg>>8) & 3;
        sysinfo->sbbusn = 0;
        sysinfo->nodes = nodes;
@@ -737,7 +735,7 @@ static int ht_setup_chains_x(void)
 
        next_busn=0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/
 
-#if K8_ALLOCATE_IO_RANGE == 1
+#if CONFIG_K8_ALLOCATE_IO_RANGE
        /* io range allocation */
        tempreg = 0 | (((reg>>8) & 0x3) << 4 )|  (0x3<<12); //limit
        pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4, tempreg);
@@ -750,7 +748,7 @@ static int ht_setup_chains_x(void)
        for(ht_c_num=1;ht_c_num<4; ht_c_num++) {
                pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0);
 
-#if K8_ALLOCATE_IO_RANGE == 1
+#if CONFIG_K8_ALLOCATE_IO_RANGE
                /* io range allocation */
                pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc4 + ht_c_num * 8, 0);
                pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc0 + ht_c_num * 8, 0);
@@ -783,7 +781,7 @@ static int ht_setup_chains_x(void)
                        pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, tempreg);
                        next_busn+=0x3f+1;
 
-#if K8_ALLOCATE_IO_RANGE == 1
+#if CONFIG_K8_ALLOCATE_IO_RANGE
                        /* io range allocation */
                        tempreg = nodeid | (linkn<<4) |  ((next_io_base+0x3)<<12); //limit
                        pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg);
@@ -807,7 +805,7 @@ static int ht_setup_chains_x(void)
                        pci_write_config32(dev, regpos, reg);
                }
 
-#if K8_ALLOCATE_IO_RANGE == 1
+#if CONFIG_K8_ALLOCATE_IO_RANGE
                /* io range allocation */
                for(i = 0; i< 4; i++) {
                        unsigned regpos;
@@ -833,7 +831,7 @@ static int ht_setup_chains_x(void)
                }
        }
 
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
        sysinfo->ht_c_num = i;
        ht_setup_chains(i, sysinfo);
        sysinfo->sbdn = get_sbdn(sysinfo->sbbusn);
@@ -843,7 +841,7 @@ static int ht_setup_chains_x(void)
 
 }
 
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
 static int optimize_link_incoherent_ht(struct sys_info *sysinfo)
 {
        // We need to use recorded link pair info to optimize the link