#include <device/pci_ids.h>
#include <device/hypertransport_def.h>
-#ifndef CONFIG_K8_HT_FREQ_1G_SUPPORT
- #define CONFIG_K8_HT_FREQ_1G_SUPPORT 0
-#endif
-
-#ifndef RAMINIT_SYSINFO
- #define RAMINIT_SYSINFO 0
-#endif
-
-#ifndef K8_ALLOCATE_IO_RANGE
- #define K8_ALLOCATE_IO_RANGE 0
-#endif
-
// Do we need allocate MMIO? Current We direct last 64M to sblink only, We can not lose access to last 4M range to ROM
#ifndef K8_ALLOCATE_MMIO_RANGE
#define K8_ALLOCATE_MMIO_RANGE 0
static inline void print_linkn_in (const char *strval, uint8_t byteval)
{
- printk(BIOS_DEBUG, "%s%02x\r\n", strval, byteval);
+ printk(BIOS_DEBUG, "%s%02x\n", strval, byteval);
}
static uint8_t ht_lookup_capability(device_t dev, uint16_t val)
return ht_lookup_capability(dev, 0); // Slave/Primary Interface Block Format
}
+#if 0
static uint8_t ht_lookup_host_capability(device_t dev)
{
return ht_lookup_capability(dev, 1); // Host/Secondary Interface Block Format
}
+#endif
static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid)
{
uint32_t id;
freq_cap = pci_read_config16(dev, pos);
- printk(BIOS_SPEW, "pos=0x%x, unfiltered freq_cap=0x%x\r\n", pos, freq_cap);
+ printk(BIOS_SPEW, "pos=0x%x, unfiltered freq_cap=0x%x\n", pos, freq_cap);
freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
id = pci_read_config32(dev, 0);
#endif
}
- printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\r\n", pos, freq_cap);
- //printk(BIOS_SPEW, "capping to 800/600/400/200 MHz\r\n");
- //freq_cap &= 0x3f;
+ printk(BIOS_SPEW, "pos=0x%x, filtered freq_cap=0x%x\n", pos, freq_cap);
+
+ #if CONFIG_SOUTHBRIDGE_VIA_K8M890 == 1
+ freq_cap &= 0x3f;
+ printk(BIOS_INFO, "Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed.\n");
+ #endif
return freq_cap;
}
int needs_reset;
/* Set link width and frequency */
- printk(BIOS_SPEW, "entering ht_optimize_link\r\n");
+ printk(BIOS_SPEW, "entering ht_optimize_link\n");
/* Initially assume everything is already optimized and I don't need a reset */
needs_reset = 0;
/* Get the frequency capabilities */
freq_cap1 = ht_read_freq_cap(dev1, pos1 + LINK_FREQ_CAP(offs1));
freq_cap2 = ht_read_freq_cap(dev2, pos2 + LINK_FREQ_CAP(offs2));
- printk(BIOS_SPEW, "freq_cap1=0x%x, freq_cap2=0x%x\r\n", freq_cap1, freq_cap2);
+ printk(BIOS_SPEW, "freq_cap1=0x%x, freq_cap2=0x%x\n", freq_cap1, freq_cap2);
/* Calculate the highest possible frequency */
freq = log2(freq_cap1 & freq_cap2);
old_freq = pci_read_config8(dev1, pos1 + LINK_FREQ(offs1));
old_freq &= 0x0f;
needs_reset |= old_freq != freq;
- printk(BIOS_SPEW, "dev1 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\r\n", old_freq, freq, needs_reset);
+ printk(BIOS_SPEW, "dev1 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\n", old_freq, freq, needs_reset);
old_freq = pci_read_config8(dev2, pos2 + LINK_FREQ(offs2));
old_freq &= 0x0f;
needs_reset |= old_freq != freq;
- printk(BIOS_SPEW, "dev2 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\r\n", old_freq, freq, needs_reset);
+ printk(BIOS_SPEW, "dev2 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\n", old_freq, freq, needs_reset);
/* Set the Calculated link frequency */
pci_write_config8(dev1, pos1 + LINK_FREQ(offs1), freq);
/* Get the width capabilities */
width_cap1 = ht_read_width_cap(dev1, pos1 + LINK_WIDTH(offs1));
width_cap2 = ht_read_width_cap(dev2, pos2 + LINK_WIDTH(offs2));
- printk(BIOS_SPEW, "width_cap1=0x%x, width_cap2=0x%x\r\n", width_cap1, width_cap2);
+ printk(BIOS_SPEW, "width_cap1=0x%x, width_cap2=0x%x\n", width_cap1, width_cap2);
/* Calculate dev1's input width */
ln_width1 = link_width_to_pow2[width_cap1 & 7];
ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7];
- printk(BIOS_SPEW, "dev1 input ln_width1=0x%x, ln_width2=0x%x\r\n", ln_width1, ln_width2);
+ printk(BIOS_SPEW, "dev1 input ln_width1=0x%x, ln_width2=0x%x\n", ln_width1, ln_width2);
if (ln_width1 > ln_width2) {
ln_width1 = ln_width2;
}
width = pow2_to_link_width[ln_width1];
- printk(BIOS_SPEW, "dev1 input width=0x%x\r\n", width);
+ printk(BIOS_SPEW, "dev1 input width=0x%x\n", width);
/* Calculate dev1's output width */
ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7];
ln_width2 = link_width_to_pow2[width_cap2 & 7];
- printk(BIOS_SPEW, "dev1 output ln_width1=0x%x, ln_width2=0x%x\r\n", ln_width1, ln_width2);
+ printk(BIOS_SPEW, "dev1 output ln_width1=0x%x, ln_width2=0x%x\n", ln_width1, ln_width2);
if (ln_width1 > ln_width2) {
ln_width1 = ln_width2;
}
width |= pow2_to_link_width[ln_width1] << 4;
- printk(BIOS_SPEW, "dev1 input|output width=0x%x\r\n", width);
+ printk(BIOS_SPEW, "dev1 input|output width=0x%x\n", width);
/* See if I am changing dev1's width */
old_width = pci_read_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1);
old_width &= 0x77;
needs_reset |= old_width != width;
- printk(BIOS_SPEW, "old dev1 input|output width=0x%x\r\n", width);
+ printk(BIOS_SPEW, "old dev1 input|output width=0x%x\n", width);
/* Set dev1's widths */
pci_write_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1, width);
/* Calculate dev2's width */
width = ((width & 0x70) >> 4) | ((width & 0x7) << 4);
- printk(BIOS_SPEW, "dev2 input|output width=0x%x\r\n", width);
+ printk(BIOS_SPEW, "dev2 input|output width=0x%x\n", width);
/* See if I am changing dev2's width */
old_width = pci_read_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1);
old_width &= 0x77;
needs_reset |= old_width != width;
- printk(BIOS_SPEW, "old dev2 input|output width=0x%x\r\n", width);
+ printk(BIOS_SPEW, "old dev2 input|output width=0x%x\n", width);
/* Set dev2's widths */
pci_write_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1, width);
return needs_reset;
}
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid, struct sys_info *sysinfo)
#else
static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid)
uint8_t next_unitid, last_unitid;
unsigned uoffs;
-#if RAMINIT_SYSINFO == 0
+#if !CONFIG_RAMINIT_SYSINFO
int reset_needed = 0;
#endif
print_err("udev="); print_err_hex32(udev);
print_err("\tupos="); print_err_hex32(upos);
print_err("\tuoffs="); print_err_hex32(uoffs);
- print_err("\tHT link capability not found\r\n");
+ print_err("\tHT link capability not found\n");
break;
}
flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
offs = ((flags>>10) & 1) ? PCI_HT_SLAVE1_OFFS : PCI_HT_SLAVE0_OFFS;
- #if RAMINIT_SYSINFO == 1
+ #if CONFIG_RAMINIT_SYSINFO
/* store the link pair here and we will Setup the Hypertransport link later, after we get final FID/VID */
{
struct link_pair_st *link_pair = &sysinfo->link_pair[sysinfo->link_pair_num];
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used ) {
uint16_t flags;
- int i;
flags = pci_read_config16(PCI_DEV(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
flags &= ~0x1f;
flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f;
pci_write_config16(PCI_DEV(bus, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags);
- #if RAMINIT_SYSINFO == 1
+ #if CONFIG_RAMINIT_SYSINFO
// Here need to change the dev in the array
+ int i;
for(i=0;i<sysinfo->link_pair_num;i++)
{
struct link_pair_st *link_pair = &sysinfo->link_pair[i];
}
#endif
-#if RAMINIT_SYSINFO == 0
+#if !CONFIG_RAMINIT_SYSINFO
return reset_needed;
#endif
}
-#if RAMINIT_SYSINFO == 1
+#if 0
+#if CONFIG_RAMINIT_SYSINFO
static void ht_setup_chain(device_t udev, unsigned upos, struct sys_info *sysinfo)
#else
static int ht_setup_chain(device_t udev, unsigned upos)
offset_unitid = 1;
#endif
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
ht_setup_chainx(udev, upos, 0, offset_unitid, sysinfo);
#else
return ht_setup_chainx(udev, upos, 0, offset_unitid);
#endif
}
+#endif
+
static int optimize_link_read_pointer(uint8_t node, uint8_t linkn, uint8_t linkt, uint8_t val)
{
uint32_t dword, dword_old;
return reset_needed;
}
+#if CONFIG_SOUTHBRIDGE_NVIDIA_CK804 // || CONFIG_SOUTHBRIDGE_NVIDIA_MCP55
static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, unsigned val)
{
uint32_t dword;
return 0;
}
+
static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val)
{
int reset_needed;
return reset_needed;
}
+#endif
-
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
static void ht_setup_chains(uint8_t ht_c_num, struct sys_info *sysinfo)
#else
static int ht_setup_chains(uint8_t ht_c_num)
device_t udev;
uint8_t i;
-#if RAMINIT_SYSINFO == 0
+#if !CONFIG_RAMINIT_SYSINFO
int reset_needed = 0;
#else
sysinfo->link_pair_num = 0;
upos = ((reg & 0xf00)>>8) * 0x20 + 0x80;
udev = PCI_DEV(0, devpos, 0);
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
ht_setup_chainx(udev,upos,busn, offset_unitid, sysinfo); // all not
#else
reset_needed |= ht_setup_chainx(udev,upos,busn, offset_unitid); //all not
}
-#if RAMINIT_SYSINFO == 0
+#if !CONFIG_RAMINIT_SYSINFO
reset_needed |= optimize_link_read_pointers_chain(ht_c_num);
return reset_needed;
static inline unsigned get_nodes(void);
#endif
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
static void ht_setup_chains_x(struct sys_info *sysinfo)
#else
static int ht_setup_chains_x(void)
uint8_t next_busn;
uint8_t ht_c_num;
uint8_t nodes;
-#if K8_ALLOCATE_IO_RANGE == 1
+#if CONFIG_K8_ALLOCATE_IO_RANGE
unsigned next_io_base;
#endif
reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
/* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn=0x3f+1 */
print_linkn_in("SBLink=", ((reg>>8) & 3) );
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
sysinfo->sblk = (reg>>8) & 3;
sysinfo->sbbusn = 0;
sysinfo->nodes = nodes;
next_busn=0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/
-#if K8_ALLOCATE_IO_RANGE == 1
+#if CONFIG_K8_ALLOCATE_IO_RANGE
/* io range allocation */
tempreg = 0 | (((reg>>8) & 0x3) << 4 )| (0x3<<12); //limit
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4, tempreg);
for(ht_c_num=1;ht_c_num<4; ht_c_num++) {
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0);
-#if K8_ALLOCATE_IO_RANGE == 1
+#if CONFIG_K8_ALLOCATE_IO_RANGE
/* io range allocation */
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc4 + ht_c_num * 8, 0);
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc0 + ht_c_num * 8, 0);
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, tempreg);
next_busn+=0x3f+1;
-#if K8_ALLOCATE_IO_RANGE == 1
+#if CONFIG_K8_ALLOCATE_IO_RANGE
/* io range allocation */
tempreg = nodeid | (linkn<<4) | ((next_io_base+0x3)<<12); //limit
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg);
pci_write_config32(dev, regpos, reg);
}
-#if K8_ALLOCATE_IO_RANGE == 1
+#if CONFIG_K8_ALLOCATE_IO_RANGE
/* io range allocation */
for(i = 0; i< 4; i++) {
unsigned regpos;
}
}
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
sysinfo->ht_c_num = i;
ht_setup_chains(i, sysinfo);
sysinfo->sbdn = get_sbdn(sysinfo->sbbusn);
}
-#if RAMINIT_SYSINFO == 1
+#if CONFIG_RAMINIT_SYSINFO
static int optimize_link_incoherent_ht(struct sys_info *sysinfo)
{
// We need to use recorded link pair info to optimize the link
unsigned link_pair_num = sysinfo->link_pair_num;
- printk(BIOS_SPEW, "entering optimize_link_incoherent_ht\r\n");
- printk(BIOS_SPEW, "sysinfo->link_pair_num=0x%x\r\n", link_pair_num);
+ printk(BIOS_SPEW, "entering optimize_link_incoherent_ht\n");
+ printk(BIOS_SPEW, "sysinfo->link_pair_num=0x%x\n", link_pair_num);
for(i=0; i< link_pair_num; i++) {
struct link_pair_st *link_pair= &sysinfo->link_pair[i];
reset_needed |= ht_optimize_link(link_pair->udev, link_pair->upos, link_pair->uoffs, link_pair->dev, link_pair->pos, link_pair->offs);
- printk(BIOS_SPEW, "after ht_optimize_link for link pair %d, reset_needed=0x%x\r\n", i, reset_needed);
+ printk(BIOS_SPEW, "after ht_optimize_link for link pair %d, reset_needed=0x%x\n", i, reset_needed);
}
reset_needed |= optimize_link_read_pointers_chain(sysinfo->ht_c_num);
- printk(BIOS_SPEW, "after optimize_link_read_pointers_chain, reset_needed=0x%x\r\n", reset_needed);
+ printk(BIOS_SPEW, "after optimize_link_read_pointers_chain, reset_needed=0x%x\n", reset_needed);
return reset_needed;
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