/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
#define NODE_MP(x) NODE_PCI(x,1)
#define NODE_MC(x) NODE_PCI(x,3)
#define NODE_LC(x) NODE_PCI(x,4)
+
static u32 get_nodes(void)
{
device_t dev;
return nodes;
}
-static void enable_apic_ext_id(u32 node)
-{
- u32 val;
- val = pci_read_config32(NODE_HT(node), 0x68);
- val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
- pci_write_config32(NODE_HT(node), 0x68, val);
-}
-
-static void setup_link_trans_cntrl()
+/**
+ * void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0)
+ */
+void AMD_CB_EventNotify (u8 evtClass, u16 event, u8 *pEventData0)
{
- /* FIXME: Not sure that this belongs here but it is HT related */
- u32 val;
- val = pci_read_config32(NODE_HT(0), 0x68);
- val |= 0x00206800; // DSNpReqLimit, LimitCldtCfg, BufRefPri, RespPassPW per BKDG;
- pci_write_config32(NODE_HT(0), 0x68, val);
-}
+ u8 i;
+ printk_debug("AMD_CB_EventNotify()\n");
+ printk_debug(" event class: %02x\n event: %04x\n data: ", evtClass, event);
+
+ for (i = 0; i < *pEventData0; i++) {
+ printk_debug(" %02x ", *(pEventData0 + i));
+ }
+ printk_debug("\n");
+}
/**
- * void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0)
+ * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
+ * Description:
+ * This routine is called every time a non-coherent chain is processed.
+ * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
+ * swap list. The first part of the list controls the BUID assignment and the
+ * second part of the list provides the device to device linking. Device orientation
+ * can be detected automatically, or explicitly. See documentation for more details.
*
- * Needs to be fixed to output the debug structures.
+ * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
+ * based on each device's unit count.
*
+ * Parameters:
+ * @param[in] u8 node = The node on which this chain is located
+ * @param[in] u8 link = The link on the host for this chain
+ * @param[out] u8** list = supply a pointer to a list
+ * @param[out] BOOL result = true to use a manual list
+ * false to initialize the link automatically
*/
-void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0)
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u16 link, u8 **List)
{
- printk_debug("AMD_CB_EventNotify()\n");
- printk_debug("event class: %02x event: %04x\n", evtClass, event);
-
+ u8 swaplist[] = { 0xFF, HT_CHAIN_UNITID_BASE, HT_CHAIN_END_UNITID_BASE, 0xFF };
+ /* If the BUID was adjusted in early_ht we need to do the manual override */
+ if ((HT_CHAIN_UNITID_BASE != 0) && (HT_CHAIN_END_UNITID_BASE != 0)) {
+ printk_debug("AMD_CB_ManualBUIDSwapList()\n");
+ if ((node == 0) && (link == 0)) { /* BSP SB link */
+ *List = swaplist;
+ return 1;
+ }
+ }
+
+ return 0;
}
+
/**
* void getAmdTopolist(u8 ***p)
*
*/
void amd_ht_init(struct sys_info *sysinfo)
{
+
AMD_HTBLOCK ht_wrapper = {
NULL, // u8 **topolist;
0, // u8 AutoBusStart;
6, // u8 AutoBusIncrement;
NULL, // BOOL (*AMD_CB_IgnoreLink)();
NULL, // BOOL (*AMD_CB_OverrideBusNumbers)();
- NULL, // BOOL (*AMD_CB_ManualBUIDSwapList)();
+ AMD_CB_ManualBUIDSwapList, // BOOL (*AMD_CB_ManualBUIDSwapList)();
NULL, // void (*AMD_CB_DeviceCapOverride)();
NULL, // void (*AMD_CB_Cpu2CpuPCBLimits)();
NULL, // void (*AMD_CB_IOPCBLimits)();