linkBase = makeLinkBase(node, link);
- // FN0_98/A4/C4 = LDT Type Register
+ /* FN0_98/A4/C4 = LDT Type Register */
AmdPCIRead(linkBase + HTHOST_LINK_TYPE_REG, &linkType);
- // Verify LinkCon=1, InitComplete=1, NC=0, UniP-cLDT=0, LinkConPend=0
+ /* Verify LinkCon=1, InitComplete=1, NC=0, UniP-cLDT=0, LinkConPend=0 */
return (linkType & HTHOST_TYPE_MASK) == HTHOST_TYPE_COHERENT;
#else
return 0;
if (pDat->HtBlock->AMD_CB_EventNotify)
{
/* Pass the node and link on which the generic synch flood event occurred. */
- sHtEventHWHtCrc evt = {sizeof(sHtEventHWHtCrc), node, link, (u8)crc};
+ sHtEventHWHtCrc evt;
+ evt.eSize = sizeof(sHtEventHWHtCrc);
+ evt.node = node;
+ evt.link = link;
+ evt.laneMask = (uint8)crc;
pDat->HtBlock->AMD_CB_EventNotify(HT_EVENT_CLASS_HW_FAULT,
HT_EVENT_HW_HTCRC,
if (pDat->HtBlock->AMD_CB_EventNotify)
{
/* Pass the node and link on which the generic synch flood event occurred. */
- sHtEventHWSynchFlood evt = {sizeof(sHtEventHWSynchFlood), node, link};
+ sHtEventHWSynchFlood evt;
+ evt.eSize = sizeof(sHtEventHWSynchFlood);
+ evt.node = node;
+ evt.link = link;
pDat->HtBlock->AMD_CB_EventNotify(HT_EVENT_CLASS_HW_FAULT,
HT_EVENT_HW_SYNCHFLOOD,
} else if (value == 4) {
return 2;
}
- STOP_HERE; // This is an error internal condition
-
- return 0xFF; // make the compiler happy.
-
+ STOP_HERE; /* This is an error internal condition */
}
/**----------------------------------------------------------------------------------------
} else if (value == 2) {
return 4;
}
- STOP_HERE; // This is an internal error condition
-
- return 0xFF; // make the compiler happy.
+ STOP_HERE; /* This is an internal error condition */
}
/**----------------------------------------------------------------------------------------
AmdPCIReadBits(linkBase + HTHOST_FREQ_REV_REG, 31, 16, &temp);
pDat->PortList[i].PrvFrequencyCap = (u16)temp & 0x7FFF
- & nb->northBridgeFreqMask(pDat->PortList[i].NodeID, pDat->nb); // Mask off bit 15, reserved value
+ & nb->northBridgeFreqMask(pDat->PortList[i].NodeID, pDat->nb); /* Mask off bit 15, reserved value */
}
else
{
ASSERT((temp >= HT_FREQUENCY_600M && temp <= HT_FREQUENCY_2600M)
|| (temp == HT_FREQUENCY_200M) || (temp == HT_FREQUENCY_400M));
AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG, 11, 8, &temp);
- if (temp > HT_FREQUENCY_1000M) // Gen1 = 200Mhz -> 1000MHz, Gen3 = 1200MHz -> 2600MHz
+ if (temp > HT_FREQUENCY_1000M) /* Gen1 = 200Mhz -> 1000MHz, Gen3 = 1200MHz -> 2600MHz */
{
/* Enable for Gen3 frequencies */
temp = 1;
{
if (pDat->HtBlock->AMD_CB_EventNotify)
{
- sHtEventOptRequiredCap evt ={sizeof(sHtEventOptRequiredCap),
- pDat->PortList[i].NodeID,
- pDat->PortList[i].HostLink,
- pDat->PortList[i].HostDepth};
+ sHtEventOptRequiredCap evt;
+ evt.eSize = sizeof(sHtEventOptRequiredCap);
+ evt.node = pDat->PortList[i].NodeID;
+ evt.link = pDat->PortList[i].HostLink;
+ evt.depth = pDat->PortList[i].HostDepth;
pDat->HtBlock->AMD_CB_EventNotify(HT_EVENT_CLASS_WARNING,
HT_EVENT_OPT_REQUIRED_CAP_RETRY,
{
if (pDat->HtBlock->AMD_CB_EventNotify)
{
- sHtEventOptRequiredCap evt ={sizeof(sHtEventOptRequiredCap),
- pDat->PortList[i].NodeID,
- pDat->PortList[i].HostLink,
- pDat->PortList[i].HostDepth};
+ sHtEventOptRequiredCap evt;
+ evt.eSize = sizeof(sHtEventOptRequiredCap);
+ evt.node = pDat->PortList[i].NodeID;
+ evt.link = pDat->PortList[i].HostLink;
+ evt.depth = pDat->PortList[i].HostDepth;
pDat->HtBlock->AMD_CB_EventNotify(HT_EVENT_CLASS_WARNING,
HT_EVENT_OPT_REQUIRED_CAP_GEN3,