Find matching settings for each CPUs FID, VID, and P-state registers and initialize...

[coreboot.git] / src / northbridge / amd / amdht / AsPsDefs.h

diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h
index 86d3375f074ac21e7cf02b76eec6d41760068919..dfc6821ed95a83c9ff6af68d1fc8ad217c67732c 100644 (file)
--- a/src/northbridge/amd/amdht/AsPsDefs.h
+++ b/src/northbridge/amd/amdht/AsPsDefs.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -21,14 +21,6 @@
 #ifndef ASPSDEFS_H
 #define ASPSDEFS_H
 
-/* AMD Platform Types */
-#define AMD_PTYPE_DSK 1
-#define AMD_PTYPE_MOB 2
-#define AMD_PTYPE_SVR 4
-#define AMD_PTYPE_DC 8
-#define AMD_PTYPE_MC 0x10
-#define AMD_PTYPE_UMA 0x20
-
 #define APIC_BAR 0x1b                  /* APIC_BAR register */
 #define APIC_BAR_BP 0x100              /* APIC_BAR BSP bit */
 
@@ -165,7 +157,10 @@
 #define CPTC1 0xd8                     /* Clock Power/Timing Control1 Register*/
 #define VSRAMP_SLAM_MASK 0xffffff88    /* MaskOff [VSRampTime]&[VSSlamTime] */
 #define VSRAMP_SLAM_VALUE 0x16         /* [VSRampTime]=001b&[VSSlamTime]=110b */
+#define VSRAMP_MASK 0xffffff8f         /* MaskOff [VSRampTime] */
+#define VSRAMP_VALUE 0x10              /* [VSRampTime]=001b */
 #define VS_RAMP_T 4                    /* VSRampTime bit position */
+#define VSSLAM_MASK 0xfffffff8         /* MaskOff [VSSlamTime] */
 #define PWR_PLN_SHIFT 28               /* PwrPlanes bit shift */
 #define PWR_PLN_ON 0x10000000          /* PwrPlanes bit ON */
 #define PWR_PLN_OFF 0x0efffffff        /* PwrPlanes bit OFF */