This patch is from 2009-10-20

[coreboot.git] / src / northbridge / amd / amdfam10 / raminit_amdmct.c

diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
index 9696689281761376013c176e4c0d89ca74fd9cb5..c9f0c27b0b2b750e9d9fdbbb2274a1f44e9baa59 100644 (file)
--- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
+++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
@@ -23,21 +23,16 @@ static  void print_raminit(const char *strval, u32 val)
        printk_debug("%s%08x\n", strval, val);
 }
 
-
-#define RAMINIT_DEBUG 1
-
-
 static  void print_tx(const char *strval, u32 val)
 {
-#if RAMINIT_DEBUG == 1
+#if CONFIG_DEBUG_RAM_SETUP
        print_raminit(strval, val);
 #endif
 }
 
-
 static  void print_t(const char *strval)
 {
-#if RAMINIT_DEBUG == 1
+#if CONFIG_DEBUG_RAM_SETUP
        print_debug(strval);
 #endif
 }
@@ -63,10 +58,10 @@ static  void print_t(const char *strval)
 #include "../amdmct/mct/mctndi_d.c"
 #include "../amdmct/mct/mctchi_d.c"
 
-#if SYSTEM_TYPE == SERVER
+#if CONFIG_CPU_SOCKET_TYPE == 0x10
 //L1
 #include "../amdmct/mct/mctardk3.c"
-#elif SYSTEM_TYPE == DESKTOP
+#elif CONFIG_CPU_SOCKET_TYPE == 0x11
 //AM2
 #include "../amdmct/mct/mctardk4.c"
 //#elif SYSTEM_TYPE == MOBILE
@@ -84,7 +79,7 @@ int mctRead_SPD(u32 smaddr, u32 reg)
 
 void mctSMBhub_Init(u32 node)
 {
-       struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+       struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
        struct mem_controller *ctrl = &( sysinfo->ctrl[node] );
        activate_spd_rom(ctrl);
 }
@@ -93,7 +88,7 @@ void mctSMBhub_Init(u32 node)
 void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node)
 {
        int j;
-       struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+       struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
        struct mem_controller *ctrl = &( sysinfo->ctrl[node] );
 
        for(j=0;j<DIMM_SOCKETS;j++) {
@@ -149,6 +144,12 @@ u32 mctGetLogicalCPUID(u32 Node)
        case 0x10023:
                ret = AMD_DR_B3;
                break;
+       case 0x10042:
+               ret = AMD_RB_C2;
+               break;
+       case 0x10062:
+               ret = AMD_DA_C2;
+               break;
        default:
                /* FIXME: mabe we should die() here. */
                print_err("FIXME! CPU Version unknown or not supported! \n");