amdfam10: add phenom II as known cpu

[coreboot.git] / src / northbridge / amd / amdfam10 / misc_control.c

diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c
index 634fec53ce3d5fc217008258eb2aa6b47b161667..472382c9a7cc5ab9e5c5f397340a57004231715e 100644 (file)
--- a/src/northbridge/amd/amdfam10/misc_control.c
+++ b/src/northbridge/amd/amdfam10/misc_control.c
@@ -30,7 +30,6 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
-#include <part/hard_reset.h>
 #include <pc80/mc146818rtc.h>
 #include <bitops.h>
 #include <cpu/amd/model_10xxx_rev.h>
@@ -59,7 +58,7 @@ static void mcf3_read_resources(device_t dev)
        pci_dev_read_resources(dev);
 
        /* If we are not the first processor don't allocate the gart apeture */
-       if (dev->path.pci.devfn != PCI_DEVFN(CDB, 3)) {
+       if (dev->path.pci.devfn != PCI_DEVFN(CONFIG_CDB, 3)) {
                return;
        }
 
@@ -69,7 +68,7 @@ static void mcf3_read_resources(device_t dev)
        if (iommu) {
                /* Add a Gart apeture resource */
                resource = new_resource(dev, 0x94);
-               resource->size = iommu?AGP_APERTURE_SIZE:1;
+               resource->size = iommu?CONFIG_AGP_APERTURE_SIZE:1;
                resource->align = log2(resource->size);
                resource->gran  = log2(resource->size);
                resource->limit = 0xffffffff; /* 4G */
@@ -126,7 +125,7 @@ static void misc_control_init(struct device *dev)
 {
        u32 cmd;
 
-       printk_debug("NB: Function 3 Misc Control.. ");
+       printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. ");
 
        /* Disable Machine checks from Invalid Locations.
         * This is needed for PC backwards compatibility.
@@ -135,7 +134,7 @@ static void misc_control_init(struct device *dev)
        cmd |= (1<<6) | (1<<25);
        pci_write_config32(dev, 0x44, cmd );
 
-       printk_debug("done.\n");
+       printk(BIOS_DEBUG, "done.\n");
 }
 
 
@@ -148,7 +147,7 @@ static struct device_operations mcf3_ops  = {
        .ops_pci          = 0,
 };
 
-static struct pci_driver mcf3_driver __pci_driver = {
+static const struct pci_driver mcf3_driver __pci_driver = {
        .ops    = &mcf3_ops,
        .vendor = PCI_VENDOR_ID_AMD,
        .device = 0x1203,