amdfam10: add phenom II as known cpu

[coreboot.git] / src / northbridge / amd / amdfam10 / debug.c

diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c
index 826b83ac0e98530090c5a7be6cf1752e22132273..2dc54275fd1b4cad1bcbe0c38e3861855f6541c8 100644 (file)
--- a/src/northbridge/amd/amdfam10/debug.c
+++ b/src/northbridge/amd/amdfam10/debug.c
@@ -21,14 +21,13 @@
  * Generic FAM10 debug code, used by mainboard specific romstage.c
  */
 
-#include "amdfam10_pci.c"
+#include "pci.c"
+#include <delay.h>
 
-static void udelay_tsc(u32 us);
-
-static  void print_debug_addr(const char *str, void *val)
+static inline void print_debug_addr(const char *str, void *val)
 {
-#if CACHE_AS_RAM_ADDRESS_DEBUG == 1
-               printk(BIOS_DEBUG, "------Address debug: %s%x------\n", str, val);
+#if CONFIG_DEBUG_CAR
+               printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val);
 #endif
 }
 
@@ -41,7 +40,7 @@ static void print_debug_pci_dev(u32 dev)
 #endif
 }
 
-static void print_pci_devices(void)
+static inline void print_pci_devices(void)
 {
        device_t dev;
        for(dev = PCI_DEV(0, 0, 0);
@@ -66,7 +65,7 @@ static void print_pci_devices(void)
        }
 }
 
-static void print_pci_devices_on_bus(u32 busn)
+static inline void print_pci_devices_on_bus(u32 busn)
 {
        device_t dev;
        for(dev = PCI_DEV(busn, 0, 0);
@@ -91,8 +90,6 @@ static void print_pci_devices_on_bus(u32 busn)
        }
 }
 
-
-
 static void dump_pci_device_range(u32 dev, u32 start_reg, u32 size)
 {
        int i;
@@ -113,11 +110,12 @@ static void dump_pci_device_range(u32 dev, u32 start_reg, u32 size)
        }
        print_debug("\n");
 }
+
 static void dump_pci_device(u32 dev)
 {
        dump_pci_device_range(dev, 0, 4096);
 }
-static u32 pci_read_config32_index_wait(device_t dev, u32 index_reg, u32 index);
+
 static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start,
                                        u32 size)
 {
@@ -139,16 +137,16 @@ static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start,
        }
        print_debug("\n");
 }
-static void dump_pci_device_index_wait(u32 dev, u32 index_reg)
+
+static inline void dump_pci_device_index_wait(u32 dev, u32 index_reg)
 {
        dump_pci_device_index_wait_range(dev, index_reg, 0, 0x54);
        dump_pci_device_index_wait_range(dev, index_reg, 0x100, 0x08); //DIMM1 when memclk > 400Hz
 //     dump_pci_device_index_wait_range(dev, index_reg, 0x200, 0x08); //DIMM2
 //     dump_pci_device_index_wait_range(dev, index_reg, 0x300, 0x08); //DIMM3
-
 }
 
-static void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length)
+static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length)
 {
        int i;
        print_debug_pci_dev(dev);
@@ -168,8 +166,7 @@ static void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length)
        print_debug("\n");
 }
 
-
-static void dump_pci_devices(void)
+static inline void dump_pci_devices(void)
 {
        device_t dev;
        for(dev = PCI_DEV(0, 0, 0);
@@ -194,8 +191,7 @@ static void dump_pci_devices(void)
        }
 }
 
-
-static void dump_pci_devices_on_bus(u32 busn)
+static inline void dump_pci_devices_on_bus(u32 busn)
 {
        device_t dev;
        for(dev = PCI_DEV(busn, 0, 0);
@@ -293,11 +289,11 @@ static void dump_smbus_registers(void)
        }
 }
 #endif
-static void dump_io_resources(u32 port)
+static inline void dump_io_resources(u32 port)
 {
 
        int i;
-       udelay_tsc(2000);
+       udelay(2000);
        printk(BIOS_DEBUG, "%04x:\n", port);
        for(i=0;i<256;i++) {
                u8 val;
@@ -313,7 +309,7 @@ static void dump_io_resources(u32 port)
        }
 }
 
-static void dump_mem(u32 start, u32 end)
+static inline void dump_mem(u32 start, u32 end)
 {
        u32 i;
        print_debug("dump_mem:");