#define NonCoherent (1 << 2)
#define ConnectionPending (1 << 4)
+// Use the LAPIC timer count register to hold each core's init status
+// Format: byte 0 - state
+// byte 1 - fid_max
+// byte 2 - nb_cof_vid_update
+// byte 3 - apic id
-#include "amdfam10_nums.h"
+#define LAPIC_MSG_REG 0x380
+#define F10_APSTATE_STARTED 0x13 // start of AP execution
+#define F10_APSTATE_STOPPED 0x14 // allow AP to stop
+#define F10_APSTATE_RESET 0x01 // waiting for warm reset
+
+#include "nums.h"
#ifdef __PRE_RAM__
#if NODE_NUMS==64
u8 rsv[1];
} __attribute__((packed));
#else
-#include "../amdmct/mct/mct_d.h"
+ #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
+ #include "../amdmct/mct_ddr3/mct_d.h"
+ #else
+ #include "../amdmct/mct/mct_d.h"
+ #endif
#endif
struct link_pair_t {
} __attribute__((packed));
+#ifndef __PRE_RAM__
+device_t get_node_pci(u32 nodeid, u32 fn);
+#endif
+
#if CONFIG_AMDMCT == 0
#ifdef __PRE_RAM__
#endif
+#ifdef __PRE_RAM__
+void showallroutes(int level, device_t dev);
+
+void setup_resource_map_offset(const u32 *register_values, u32 max, u32
+ offset_pci_dev, u32 offset_io_base);
+
+void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32
+ offset_pci_dev, u32 offset_io_base);
+
+void setup_resource_map_x(const u32 *register_values, u32 max);
+
+/* reset_test.c */
+u32 cpu_init_detected(u8 nodeid);
+u32 bios_reset_detected(void);
+u32 cold_reset_detected(void);
+u32 other_reset_detected(void);
+u32 get_sblk(void);
+u8 get_sbbusn(u8 sblk);
+#endif
+
+#include "northbridge/amd/amdht/porting.h"
+BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, const u8 **List);
+
#endif /* AMDFAM10_H */