Simplify a few code chunks, fix whitespace and indentation.
[coreboot.git] / src / mainboard / via / epia-n / romstage.c
index 1b4e27a7afa92ee9ed188c04c35a1a95fe6e190e..90d92383ad6fde4349b4e036c8bcb291d2218e2a 100644 (file)
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
 #include "superio/winbond/w83697hf/w83697hf_early_serial.c"
+#include <spd.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
 
-/*
- * NOOB ::
- * d0f0 - Device 0 Function 0 etc.
- */
 static const struct mem_controller ctrl = {
        .d0f0 = 0x0000,
        .d0f2 = 0x2000,
@@ -65,7 +62,8 @@ static void enable_mainboard_devices(void)
        device_t dev;
        u8 reg;
 
-       dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+       dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+                               PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
        if (dev == PCI_DEV_INVALID)
                die("Southbridge not found!!!\n");
 
@@ -113,14 +111,10 @@ static void main(unsigned long bist)
        pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
 
        w83697hf_set_clksel_48(SERIAL_DEV);
-
        w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
        uart_init();
        console_init();
 
-       print_spew("In romstage.c:main()\n");
-
        enable_smbus();
        smbus_fixup(&ctrl);
 
@@ -133,19 +127,13 @@ static void main(unsigned long bist)
        print_debug("Enable F-ROM Shadow RAM\n");
        enable_shadow_ram();
 
-       /* setup cpu */
        print_debug("Setup CPU Interface\n");
        c3_cpu_setup(ctrl.d0f2);
 
        ddr_ram_setup();
 
-       if (bist == 0) {
-               print_debug("doing early_mtrr\n");
+       if (bist == 0)
                early_mtrr_init();
-       }
 
        //ram_check(0, 640 * 1024);
-
-       print_spew("Leaving romstage.c:main()\n");
 }
-