- Update abuild.sh so it will rebuild successfull builds

[coreboot.git] / src / mainboard / via / epia-m / auto.c

diff --git a/src/mainboard/via/epia-m/auto.c b/src/mainboard/via/epia-m/auto.c
index 88523ed9e91d7c000f28d0165d3b0a5e82b06b1e..79dbb27867f5162fd7ae4481741ca25eef6d8b86 100644 (file)
--- a/src/mainboard/via/epia-m/auto.c
+++ b/src/mainboard/via/epia-m/auto.c
@@ -3,7 +3,9 @@
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
-#include <cpu/p6/apic.h>
+#if 0
+#include <cpu/x86/lapic.h>
+#endif
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
@@ -12,7 +14,8 @@
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
 #include "northbridge/via/vt8623/raminit.h"
-#include "cpu/p6/earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
 
 /*
  */
@@ -24,7 +27,7 @@ void udelay(int usecs)
 }
 
 #include "lib/delay.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
 #include "debug.c"
 
 #include "southbridge/via/vt8235/vt8235_early_smbus.c"
@@ -49,7 +52,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 
 
-#include "northbridge/via/vt8601/raminit.c"
+#include "northbridge/via/vt8623/raminit.c"
 /*
   #include "sdram/generic_sdram.c"
 */
@@ -64,8 +67,9 @@ static void enable_mainboard_devices(void)
        if (dev == PCI_DEV_INVALID) {
                die("Southbridge not found!!!\n");
        }
-       pci_write_config8(dev, 0x50, 7);
-       pci_write_config8(dev, 0x51, 0xff);
+       pci_write_config8(dev, 0x50, 0);
+       pci_write_config8(dev, 0x51, 0xfd);
+       pci_write_config8(dev, 0x94, 0xb2);
 #if 0
        // This early setup switches IDE into compatibility mode before PCI gets 
        // // a chance to assign I/Os
@@ -94,17 +98,32 @@ static void enable_shadow_ram(void)
        pci_write_config8(dev, 0x63, shadowreg);
 }
 
-static void main(void)
+static void main(unsigned long bist)
 {
        unsigned long x;
+       device_t dev;
+
+       if (bist == 0) {
+               early_mtrr_init();
+       }
+       enable_vt8235_serial();
+       uart_init();
+       console_init();
+
+
+       /* Halt if there was a built in self test failure */
+       report_bist_failure(bist);
+
        /*      init_timer();*/
        outb(5, 0x80);
+
        
+       pci_write_config8( 0xd*8,0x15,0x1c);
+       pci_write_config8( 0 , 0xe1, 0xdd);
+ 
+       outb(5, 0x80);  
        enable_smbus();
-       enable_vt8235_serial();
 
-       uart_init();
-       console_init();
        
        enable_mainboard_devices();
        enable_shadow_ram();
@@ -137,5 +156,4 @@ static void main(void)
                ram_check(check_addrs[i].lo, check_addrs[i].hi);
        }
 #endif
-       early_mtrr_init();
 }