uses HAVE_HARD_RESET
uses HAVE_OPTION_TABLE
uses USE_OPTION_TABLE
-uses CONFIG_ROM_STREAM
+uses CONFIG_ROM_PAYLOAD
uses IRQ_SLOT_COUNT
uses MAINBOARD
uses MAINBOARD_VENDOR
uses MAINBOARD_PART_NUMBER
-uses LINUXBIOS_EXTRA_VERSION
+uses COREBOOT_EXTRA_VERSION
uses ARCH
uses FALLBACK_SIZE
uses STACK_SIZE
uses ROM_IMAGE_SIZE
uses ROM_SECTION_SIZE
uses ROM_SECTION_OFFSET
-uses CONFIG_ROM_STREAM_START
-uses CONFIG_COMPRESSED_ROM_STREAM
+uses CONFIG_ROM_PAYLOAD_START
+uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses CONFIG_PRECOMPRESSED_PAYLOAD
uses PAYLOAD_SIZE
uses _ROMBASE
uses _RAMBASE
uses MAXIMUM_CONSOLE_LOGLEVEL
uses CONFIG_CONSOLE_SERIAL8250
uses CONFIG_UDELAY_TSC
+uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
uses CONFIG_PCI_ROM_RUN
uses CONFIG_CONSOLE_VGA
uses CONFIG_MAX_PCI_BUSES
## Use TSC for udelay.
##
default CONFIG_UDELAY_TSC=1
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
##
-## Build code to reset the motherboard from linuxBIOS
+## Build code to reset the motherboard from coreboot
##
-default HAVE_HARD_RESET=1
+default HAVE_HARD_RESET=0
##
## Build code to export a programmable irq routing table
default HAVE_OPTION_TABLE=1
###
-### LinuxBIOS layout values
+### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default ROM_IMAGE_SIZE = 65536
default FALLBACK_SIZE = 131072
default _RAMBASE = 0x00004000
-default CONFIG_ROM_STREAM = 1
+default CONFIG_ROM_PAYLOAD = 1
##
## The default compiler
##
default CONFIG_MAX_PCI_BUSES = 5
+default MAXIMUM_CONSOLE_LOGLEVEL=8
+default DEFAULT_CONSOLE_LOGLEVEL=8
+default CONFIG_CONSOLE_SERIAL8250=1
+
end