Move files from src/cpu/x86/{fpu,mmx,sse}/ to x86/

[coreboot.git] / src / mainboard / via / epia-m / Config.lb

diff --git a/src/mainboard/via/epia-m/Config.lb b/src/mainboard/via/epia-m/Config.lb
index a3e4b4148665de6c8f4e6851143245403ebd2a37..d6924bd7824eee7b5270df2f384e467d6a6db173 100644 (file)
--- a/src/mainboard/via/epia-m/Config.lb
+++ b/src/mainboard/via/epia-m/Config.lb
@@ -1,36 +1,7 @@
-##
-## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-       default ROM_SECTION_SIZE   = FALLBACK_SIZE
-       default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-       default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-       default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The linuxBIOS bootloader.
-##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of linuxBIOS will start in the boot rom
-##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 128 * 1024
+include /config/nofailovercalculation.lb
+default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
 
 ##
 ## Set all of the defaults for an x86 architecture
@@ -43,11 +14,11 @@ arch i386 end
 ##
 
 driver mainboard.o
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
 object vgabios.o
 
-if HAVE_ACPI_TABLES
+if CONFIG_GENERATE_ACPI_TABLES
        object fadt.o
        object dsdt.o
        object acpi_tables.o
@@ -57,26 +28,26 @@ end
 ## Romcc output
 ##
 makerule ./failover.E
-       depends "$(MAINBOARD)/failover.c ./romcc" 
-       action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+       depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" 
+       action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-       depends "$(MAINBOARD)/failover.c ./romcc"
-       action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+       depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
+       action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-       depends "$(MAINBOARD)/auto.c option_table.h ./romcc" 
-       action  "./romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+       depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
+       action  "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-       depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-       action  "./romcc    -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+       depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
+       action  "../romcc    -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -84,9 +55,9 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
-if USE_FALLBACK_IMAGE 
+if CONFIG_USE_FALLBACK_IMAGE 
        mainboardinit cpu/x86/16bit/reset16.inc 
        ldscript /cpu/x86/16bit/reset16.lds 
 else
@@ -104,11 +75,11 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
        ldscript /arch/i386/lib/failover.lds 
        mainboardinit ./failover.inc
 end
@@ -120,10 +91,9 @@ end
 ##
 ## Setup RAM
 ##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit cpu/x86/fpu_enable.inc
 mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
+mainboardinit cpu/x86/mmx_disable.inc
 
 ##
 ## Include the secondary Configuration files 
@@ -134,7 +104,7 @@ config chip.h
 chip northbridge/via/vt8623
 
        device apic_cluster 0 on
-               chip cpu/via/model_centaur
+               chip cpu/via/model_c3
                        device apic 0 on  end 
                end
        end