Thanks to Myles' patch adding support for include statements,

[coreboot.git] / src / mainboard / via / epia-m / Config.lb

diff --git a/src/mainboard/via/epia-m/Config.lb b/src/mainboard/via/epia-m/Config.lb
index decbd0e3b1f2fe8ba43858950c50eb68423ab9b8..2848c474ead084fb6ad4e372218e69f8eca9d9c7 100644 (file)
--- a/src/mainboard/via/epia-m/Config.lb
+++ b/src/mainboard/via/epia-m/Config.lb
@@ -1,36 +1,4 @@
-##
-## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-       default ROM_SECTION_SIZE   = FALLBACK_SIZE
-       default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-       default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-       default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The linuxBIOS bootloader.
-##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of linuxBIOS will start in the boot rom
-##
-default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+include /config/nofailovercalculation.lb
 
 ##
 ## Set all of the defaults for an x86 architecture
@@ -45,6 +13,7 @@ arch i386 end
 driver mainboard.o
 if HAVE_PIRQ_TABLE object irq_tables.o end
 #object reset.o
+object vgabios.o
 
 if HAVE_ACPI_TABLES
        object fadt.o
@@ -56,26 +25,26 @@ end
 ## Romcc output
 ##
 makerule ./failover.E
-       depends "$(MAINBOARD)/failover.c ./romcc" 
-       action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+       depends "$(MAINBOARD)/failover.c ../romcc" 
+       action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./failover.inc
-       depends "$(MAINBOARD)/failover.c ./romcc"
-       action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+       depends "$(MAINBOARD)/failover.c ../romcc"
+       action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
 end
 
 makerule ./auto.E 
-       depends "$(MAINBOARD)/auto.c option_table.h ./romcc" 
-       action  "./romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+       depends "$(MAINBOARD)/auto.c option_table.h ../romcc" 
+       action  "../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 makerule ./auto.inc 
-       depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
-       action  "./romcc    -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+       depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+       action  "../romcc    -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
 ##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
 ##
 mainboardinit cpu/x86/16bit/entry16.inc
 mainboardinit cpu/x86/32bit/entry32.inc
@@ -83,7 +52,7 @@ ldscript /cpu/x86/16bit/entry16.lds
 ldscript /cpu/x86/32bit/entry32.lds
 
 ##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
 ##
 if USE_FALLBACK_IMAGE 
        mainboardinit cpu/x86/16bit/reset16.inc 
@@ -103,7 +72,7 @@ mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of coreboot startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
@@ -131,13 +100,15 @@ dir /pc80
 config chip.h
 
 chip northbridge/via/vt8623
+
+       device apic_cluster 0 on
+               chip cpu/via/model_c3
+                       device apic 0 on  end 
+               end
+       end
+
        device pci_domain 0 on
                chip southbridge/via/vt8235
-                       register "enable_usb" = "0"
-                       register "enable_native_ide" = "0"
-                       register "enable_com_ports" = "1"
-                       register "enable_keyboard" = "0"
-                       register "enable_nvram" = "1"
 
                        device pci 10.0 on end # USB 1.1
                        device pci 10.1 on end # USB 1.1
@@ -151,7 +122,7 @@ chip northbridge/via/vt8623
                                                irq 0x70 = 6
                                                drq 0x74 = 2
                                        end
-                                       device pnp 2e.1 off     # Parallel Port
+                                       device pnp 2e.1 on      # Parallel Port
                                                io 0x60 = 0x378
                                                irq 0x70 = 7
                                                drq 0x74 = 3
@@ -178,10 +149,10 @@ chip northbridge/via/vt8623
                        device pci 12.0 on end  # Ethernet
                end
 #              This is on the EPIA MII, not the M.
-#              chip southbridge/ricoh/rl5c476
-#              end
-       end
-
-       chip cpu/via/model_centaur 
+               chip southbridge/ricoh/rl5c476
+                       register "enable_cf" = "1"
+                       device pci 0a.0 on end
+                       device pci 0a.1 on end  
+               end
        end
 end