#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <stdlib.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
#include "lib/ramtest.c"
#include "northbridge/via/vt8601/raminit.h"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
#include "lib/debug.c"
#include "southbridge/via/vt8231/vt8231_early_smbus.c"
#include "southbridge/via/vt8231/vt8231_early_serial.c"
+#include "southbridge/via/vt8231/vt8231_enable_rom.c"
static inline int spd_read_byte(unsigned device, unsigned address)
{
}
#include "northbridge/via/vt8601/raminit.c"
-/*
- #include "lib/generic_sdram.c"
-*/
-static void enable_mainboard_devices(void)
+static void enable_mainboard_devices(void)
{
device_t dev;
/* dev 0 for southbridge */
-
+
dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
-
+
if (dev == PCI_DEV_INVALID) {
die("Southbridge not found!!!\n");
}
pci_write_config8(dev, 0x50, 7);
pci_write_config8(dev, 0x51, 0xff);
#if 0
- // This early setup switches IDE into compatibility mode before PCI gets
+ // This early setup switches IDE into compatibility mode before PCI gets
// a chance to assign I/Os
// movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
// movb $0x09, %dl
// PCI_WRITE_CONFIG_BYTE
//
#endif
- /* we do this here as in V2, we can not yet do raw operations
+ /* we do this here as in V2, we can not yet do raw operations
* to pci!
*/
/* changed this to work correctly on later revisions of LB.
pci_write_config8(dev, 0x42, 0);
}
-static void enable_shadow_ram(void)
+static void enable_shadow_ram(void)
{
device_t dev = 0;
unsigned char shadowreg;
static void main(unsigned long bist)
{
- unsigned long x;
-
if (bist == 0) {
early_mtrr_init();
}
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
-
+
+ vt8231_enable_rom();
enable_mainboard_devices();
enable_smbus();
enable_shadow_ram();
sdram_set_registers((const struct mem_controller *) 0);
sdram_set_spd_registers((const struct mem_controller *) 0);
sdram_enable(0, (const struct mem_controller *) 0);
-
+
/* Check all of memory */
#if 0
ram_check(0x00000000, msr.lo);
}
#endif
}
-