#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static void hard_reset(void)
-{
- device_t dev;
-
- /* Find the device */
- dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 3);
-
- set_bios_reset();
-
- /* enable cf9 */
- pci_write_config8(dev, 0x41, 0xf1);
- /* reset */
- outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
- device_t dev;
-
- /* Find the device */
- dev = PCI_DEV(node_link_to_bus(0, 1), 0x04, 0);
- set_bios_reset();
- pci_write_config8(dev, 0x47, 1);
-}
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
static void memreset_setup(void)
{
return smbus_read_byte(device, address);
}
-#define K8_4RANK_DIMM_SUPPORT 1
+#define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
};
int needs_reset;
- unsigned cpu_reset = 0;
unsigned bsp_apicid = 0;
struct mem_controller ctrl[8];
setup_s4882_resource_map();
needs_reset = setup_coherent_ht_domain();
-
+
+ wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
- wait_all_core0_started();
start_other_cores();
+ wait_all_other_cores_started(bsp_apicid);
#endif
- wait_all_aps_started(bsp_apicid);
-
// automatically set that for you, but you might meet tight space
needs_reset |= ht_setup_chains_x();
memreset_setup();
sdram_initialize(nodes, ctrl);
- post_cache_as_ram(cpu_reset);
+ post_cache_as_ram();
}