Drop excessive whitespace randomly sprinkled in romstage.c files.

[coreboot.git] / src / mainboard / tyan / s4880 / romstage.c

diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c
index 49f7f16a190ca63e7ae8d47d050a9fd3ebd38ea9..09a052fc3ca3b69865d47a27d91b56aba137ac72 100644 (file)
--- a/src/mainboard/tyan/s4880/romstage.c
+++ b/src/mainboard/tyan/s4880/romstage.c
@@ -1,6 +1,3 @@
-#define ASSEMBLY 1
-
- 
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -9,33 +6,26 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
 #include <stdlib.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "lib/ramtest.c"
-
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <lib.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
 static void memreset_setup(void)
 {
    if (is_cpu_pre_c0()) {
@@ -58,7 +48,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
 #define SMBUS_HUB 0x18
-        int ret;
         unsigned device=(ctrl->channel0[0])>>8;
         smbus_write_byte(SMBUS_HUB, 0x01, device);
         smbus_write_byte(SMBUS_HUB, 0x03, 0);
@@ -68,11 +57,11 @@ static inline void change_i2c_mux(unsigned device)
 {
 #define SMBUS_HUB 0x18
         int ret;
-        print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n"); 
+        print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
         ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
-        print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n");
+        print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
-        print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n");
+        print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
 }
 #endif
 
@@ -81,39 +70,22 @@ static inline int spd_read_byte(unsigned device, unsigned address)
        return smbus_read_byte(device, address);
 }
 
-#define QRANK_DIMM_SUPPORT 1
-
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "resourcemap.c" 
-
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
-#endif
+#include "resourcemap.c" /* tyan does not want the default */
 #include "cpu/amd/dualcore/dualcore.c"
+#include <spd.h>
+#include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/model_fxx/init_cpus.c"
+#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
 
 #define RC0 ((1<<2)<<8)
 #define RC1 ((1<<1)<<8)
 #define RC2 ((1<<4)<<8)
 #define RC3 ((1<<3)<<8)
 
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-
-#include "cpu/amd/car/copy_and_run.c"
-
-#include "cpu/amd/car/post_cache_as_ram.c"
-
-#include "cpu/amd/model_fxx/init_cpus.c"
-
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const struct mem_controller cpu[] = {
@@ -188,7 +160,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         setup_s4880_resource_map();
 
        needs_reset = setup_coherent_ht_domain();
-       
+
 #if CONFIG_LOGICAL_CPUS==1
         // It is said that we should start core1 after all core0 launched
         start_other_cores();
@@ -197,7 +169,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         needs_reset |= ht_setup_chains_x();
 
                if (needs_reset) {
-                       print_info("ht reset -\r\n");
+                       print_info("ht reset -\n");
                        soft_reset();
                }