printk_foo -> printk(BIOS_FOO, ...)

[coreboot.git] / src / mainboard / tyan / s2912_fam10 / romstage.c

diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 29e40602437524007677851dd225b7bcb26b985d..cee8c5952f7a86cea6b00641448413f533bb69ce 100644 (file)
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -198,7 +198,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
        console_init();
-       printk_debug("\n");
+       printk(BIOS_DEBUG, "\n");
 
        /* Halt if there was a built in self test failure */
        report_bist_failure(bist);
@@ -209,10 +209,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #endif
 
        val = cpuid_eax(1);
-       printk_debug("BSP Family_Model: %08x\n", val);
-       printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
-       printk_debug("bsp_apicid = %02x\n", bsp_apicid);
-       printk_debug("cpu_init_detectedx = %08x\n", cpu_init_detectedx);
+       printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+       printk(BIOS_DEBUG, "*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n");
+       printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+       printk(BIOS_DEBUG, "cpu_init_detectedx = %08x\n", cpu_init_detectedx);
 
        /* Setup sysinfo defaults */
        set_sysinfo_in_ram(0);
@@ -243,7 +243,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 #if CONFIG_LOGICAL_CPUS==1
        /* Core0 on each node is configured. Now setup any additional cores. */
-       printk_debug("start_other_cores()\n");
+       printk(BIOS_DEBUG, "start_other_cores()\n");
        start_other_cores();
        post_code(0x37);
        wait_all_other_cores_started(bsp_apicid);
@@ -253,7 +253,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 #if FAM10_SET_FIDVID == 1
        msr = rdmsr(0xc0010071);
-       printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
+       printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 
        /* FIXME: The sb fid change may survive the warm reset and only
         * need to be done once.*/
@@ -271,7 +271,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        /* show final fid and vid */
        msr=rdmsr(0xc0010071);
-       printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
+       printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 #endif
 
        wants_reset = mcp55_early_setup_x();
@@ -284,27 +284,27 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        }
 
        if (wants_reset)
-               printk_debug("mcp55_early_setup_x wanted additional reset!\n");
+               printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
 
        post_code(0x3B);
 
        /* It's the time to set ctrl in sysinfo now; */
-       printk_debug("fill_mem_ctrl()\n");
+       printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
        fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
        post_code(0x3D);
 
-       printk_debug("enable_smbus()\n");
+       printk(BIOS_DEBUG, "enable_smbus()\n");
        enable_smbus();
        post_code(0x3E);
 
        memreset_setup();
        post_code(0x40);
 
-       printk_debug("raminit_amdmct()\n");
+       printk(BIOS_DEBUG, "raminit_amdmct()\n");
        raminit_amdmct(sysinfo);
        post_code(0x41);
 
-       printk_debug("\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
+       printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
        post_cache_as_ram();    // BSP switch stack to ram, copy then execute LB.
        post_code(0x43);        // Should never see this post code.
 }