Remove a few more warnings from fam10.

[coreboot.git] / src / mainboard / tyan / s2912_fam10 / romstage.c

diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index caf6c18dac57d2afc67a943313d058448f6a9569..5f6d2a7691d217dc810876fa400d4fd749c5316c 100644 (file)
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -19,9 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
-
 #define RAMINIT_SYSINFO 1
 
 #define FAM10_SCAN_PCI_BUS 0
@@ -33,8 +30,8 @@
 #define SET_NB_CFG_54 1
 #endif
 
-#define FAM10_SET_FIDVID 1
-#define FAM10_SET_FIDVID_CORE_RANGE 0
+#define SET_FIDVID 1
+#define SET_FIDVID_CORE_RANGE 0
 
 #define DBGP_DEFAULT 7
 
@@ -49,7 +46,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
+#include "console/console.c"
 #if CONFIG_USBDEBUG_DIRECT
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
 #include "pc80/usbdebug_direct_serial.c"
@@ -71,7 +68,7 @@
 
 #include "northbridge/amd/amdfam10/debug.c"
 
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 
 #include "northbridge/amd/amdfam10/setup_resource_map.c"
 
@@ -79,14 +76,6 @@
 
 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
 
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
        /* nothing to do */
@@ -124,10 +113,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 
-#include "cpu/amd/car/copy_and_run.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
 
+#include "cpu/amd/microcode/microcode.c"
+#include "cpu/amd/model_10xxx/update_microcode.c"
 #include "cpu/amd/model_10xxx/init_cpus.c"
 
 #include "cpu/amd/model_10xxx/fidvid.c"
@@ -137,7 +126,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 static void sio_setup(void)
 {
-       unsigned value;
        uint32_t dword;
        uint8_t byte;
 
@@ -153,12 +141,9 @@ static void sio_setup(void)
        dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
        dword |= (1<<16);
        pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
-
 }
 
 #include "spd_addr.h"
-#include "cpu/amd/microcode/microcode.c"
-#include "cpu/amd/model_10xxx/update_microcode.c"
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -246,7 +231,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        post_code(0x38);
 
-#if FAM10_SET_FIDVID == 1
+#if SET_FIDVID == 1
        msr = rdmsr(0xc0010071);
        printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 
@@ -290,9 +275,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        printk(BIOS_DEBUG, "enable_smbus()\n");
        enable_smbus();
-       post_code(0x3E);
 
-       memreset_setup();
        post_code(0x40);
 
        printk(BIOS_DEBUG, "raminit_amdmct()\n");