Move "select CACHE_AS_RAM" lines from boards into CPU socket.

[coreboot.git] / src / mainboard / tyan / s2912_fam10 / Kconfig

diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig
index d1a32332827ffe20c00aa21a77ed76073eebcaee..58cdb9c83ca52e88777757b650b4a7d0af78a306 100644 (file)
--- a/src/mainboard/tyan/s2912_fam10/Kconfig
+++ b/src/mainboard/tyan/s2912_fam10/Kconfig
@@ -4,20 +4,25 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        def_bool y
        select ARCH_X86
        select CPU_AMD_SOCKET_F_1207
+       select DIMM_DDR2
+       select DIMM_REGISTERED
        select NORTHBRIDGE_AMD_AMDFAM10
        select SOUTHBRIDGE_NVIDIA_MCP55
+       select MCP55_USE_NIC
        select SUPERIO_WINBOND_W83627HF
        select HAVE_BUS_CONFIG
        select HAVE_OPTION_TABLE
        select HAVE_PIRQ_TABLE
        select HAVE_MP_TABLE
-       select USE_DCACHE_RAM
        select HAVE_HARD_RESET
        select LIFT_BSP_APIC_ID
        select BOARD_ROMSIZE_KB_1024
+       select RAMINIT_SYSINFO
        select ENABLE_APIC_EXT_ID
        select AMDMCT
        select TINY_BOOTBLOCK
+       select MMCONF_SUPPORT_DEFAULT
+       select QRANK_DIMM_SUPPORT
 
 config MAINBOARD_DIR
        string
@@ -55,10 +60,6 @@ config PCI_64BIT_PREF_MEM
        bool
        default n
 
-config HW_MEM_HOLE_SIZEK
-       hex
-       default 0x100000
-
 config MAX_CPUS
        int
        default 12
@@ -67,10 +68,6 @@ config MAX_PHYSICAL_CPUS
        int
        default 2
 
-config HW_MEM_HOLE_SIZE_AUTO_INC
-       bool
-       default n
-
 config HT_CHAIN_UNITID_BASE
        hex
        default 0x1
@@ -107,4 +104,8 @@ config HEAP_SIZE
        hex
        default 0xc0000
 
+config MCP55_PCI_E_X_0
+       int
+       default 1
+
 endif # BOARD_TYAN_S2912_FAM10