Move "select CACHE_AS_RAM" lines from boards into CPU socket.

[coreboot.git] / src / mainboard / tyan / s2912 / Kconfig

diff --git a/src/mainboard/tyan/s2912/Kconfig b/src/mainboard/tyan/s2912/Kconfig
index 2075b317e3474db4b8cbd58a5a5e70f1ea5ac968..466cb4a889149e3b115d348af2a358c7e31965e5 100644 (file)
--- a/src/mainboard/tyan/s2912/Kconfig
+++ b/src/mainboard/tyan/s2912/Kconfig
@@ -9,16 +9,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        select NORTHBRIDGE_AMD_AMDK8
        select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
        select SOUTHBRIDGE_NVIDIA_MCP55
+       select MCP55_USE_NIC
        select SUPERIO_WINBOND_W83627HF
        select HAVE_BUS_CONFIG
        select HAVE_OPTION_TABLE
        select HAVE_PIRQ_TABLE
        select HAVE_MP_TABLE
-       select CACHE_AS_RAM
        select HAVE_HARD_RESET
        select LIFT_BSP_APIC_ID
        select K8_REV_F_SUPPORT
        select BOARD_ROMSIZE_KB_512
+       select RAMINIT_SYSINFO
+       select QRANK_DIMM_SUPPORT
+       select K8_ALLOCATE_IO_RANGE
 
 config MAINBOARD_DIR
        string
@@ -56,10 +59,6 @@ config PCI_64BIT_PREF_MEM
        bool
        default n
 
-config HW_MEM_HOLE_SIZEK
-       hex
-       default 0x100000
-
 config MAX_CPUS
        int
        default 4
@@ -68,10 +67,6 @@ config MAX_PHYSICAL_CPUS
        int
        default 2
 
-config HW_MEM_HOLE_SIZE_AUTO_INC
-       bool
-       default n
-
 config HT_CHAIN_UNITID_BASE
        hex
        default 0x0
@@ -92,4 +87,8 @@ config IRQ_SLOT_COUNT
        int
        default 11
 
+config MCP55_PCI_E_X_0
+       int
+       default 1
+
 endif # BOARD_TYAN_S2912