nvidia/mcp55: Move HAVE_HARD_RESET to southbridge

[coreboot.git] / src / mainboard / tyan / s2912 / Kconfig

diff --git a/src/mainboard/tyan/s2912/Kconfig b/src/mainboard/tyan/s2912/Kconfig
index 27fcbb2cb5ce51454caad6eb684101b3a6be1312..192b4ff151c7e09bf6d1a9397ae8499804f4fa6f 100644 (file)
--- a/src/mainboard/tyan/s2912/Kconfig
+++ b/src/mainboard/tyan/s2912/Kconfig
@@ -4,19 +4,23 @@ config BOARD_SPECIFIC_OPTIONS # dummy
        def_bool y
        select ARCH_X86
        select CPU_AMD_SOCKET_F
+       select DIMM_DDR2
+       select DIMM_REGISTERED
        select NORTHBRIDGE_AMD_AMDK8
        select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
        select SOUTHBRIDGE_NVIDIA_MCP55
+       select MCP55_USE_NIC
        select SUPERIO_WINBOND_W83627HF
        select HAVE_BUS_CONFIG
        select HAVE_OPTION_TABLE
        select HAVE_PIRQ_TABLE
        select HAVE_MP_TABLE
-       select USE_DCACHE_RAM
-       select HAVE_HARD_RESET
        select LIFT_BSP_APIC_ID
        select K8_REV_F_SUPPORT
        select BOARD_ROMSIZE_KB_512
+       select RAMINIT_SYSINFO
+       select QRANK_DIMM_SUPPORT
+       select K8_ALLOCATE_IO_RANGE
 
 config MAINBOARD_DIR
        string
@@ -54,10 +58,6 @@ config PCI_64BIT_PREF_MEM
        bool
        default n
 
-config HW_MEM_HOLE_SIZEK
-       hex
-       default 0x100000
-
 config MAX_CPUS
        int
        default 4
@@ -66,10 +66,6 @@ config MAX_PHYSICAL_CPUS
        int
        default 2
 
-config HW_MEM_HOLE_SIZE_AUTO_INC
-       bool
-       default n
-
 config HT_CHAIN_UNITID_BASE
        hex
        default 0x0
@@ -82,12 +78,12 @@ config SERIAL_CPU_INIT
        bool
        default n
 
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-       hex
-       default 0x2912
-
 config IRQ_SLOT_COUNT
        int
        default 11
 
+config MCP55_PCI_E_X_0
+       int
+       default 1
+
 endif # BOARD_TYAN_S2912