Simplify a few code chunks, fix whitespace and indentation.

[coreboot.git] / src / mainboard / tyan / s2895 / romstage.c

diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c
index 00836ac2e0df9676e1093ea2a63459d6a3d81229..7a6fcbc3a79a688ac626eaf8229630631fdcf139 100644 (file)
--- a/src/mainboard/tyan/s2895/romstage.c
+++ b/src/mainboard/tyan/s2895/romstage.c
@@ -1,11 +1,3 @@
-#define K8_ALLOCATE_IO_RANGE 1
-
-#define QRANK_DIMM_SUPPORT 1
-
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
-#endif
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -16,6 +8,7 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <lib.h>
+#include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
@@ -26,38 +19,31 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
-#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
-#define SUPERIO_GPIO_IO_BASE 0x400
 #include "cpu/x86/bist.h"
 #include "northbridge/amd/amdk8/debug.c"
 #include <cpu/amd/mtrr.h>
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
 
-static void memreset_setup(void)
-{
-}
+#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
+#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
+#define SUPERIO_GPIO_IO_BASE 0x400
 
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset_setup(void) { }
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
 
 static void sio_gpio_setup(void)
 {
        unsigned value;
 
        /*Enable onboard scsi*/
-       lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
+       lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c,
+         (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
        value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
        lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
 }
 
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-       /* nothing to do */
-}
-
 static inline int spd_read_byte(unsigned device, unsigned address)
 {
        return smbus_read_byte(device, address);
@@ -66,12 +52,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
-
- /* tyan does not want the default */
 #include "resourcemap.c"
-
 #include "cpu/amd/dualcore/dualcore.c"
-
 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 
 //set GPIO to input mode
@@ -84,11 +66,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
        RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 
 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
 #include "northbridge/amd/amdk8/early_ht.c"
 
 static void sio_setup(void)
@@ -120,30 +99,25 @@ static void sio_setup(void)
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const u16 spd_addr [] = {
-               (0xa<<3)|0, (0xa<<3)|2, 0, 0,
-               (0xa<<3)|1, (0xa<<3)|3, 0, 0,
-               (0xa<<3)|4, (0xa<<3)|6, 0, 0,
-               (0xa<<3)|5, (0xa<<3)|7, 0, 0,
+               DIMM0, DIMM2, 0, 0,
+               DIMM1, DIMM3, 0, 0,
+               DIMM4, DIMM6, 0, 0,
+               DIMM5, DIMM7, 0, 0,
        };
 
        int needs_reset;
-       unsigned bsp_apicid = 0;
-
+       unsigned bsp_apicid = 0, nodes;
        struct mem_controller ctrl[8];
-       unsigned nodes;
 
        if (!cpu_init_detectedx && boot_cpu()) {
                /* Nothing special needs to be done to find bus 0 */
                /* Allow the HT devices to be found */
-
                enumerate_ht_chain();
-
                sio_setup();
        }
 
-       if (bist == 0) {
+       if (bist == 0)
                bsp_apicid = init_cpus(cpu_init_detectedx);
-       }
 
        lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
@@ -165,9 +139,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        wait_all_other_cores_started(bsp_apicid);
 
        needs_reset |= ht_setup_chains_x();
-
        needs_reset |= ck804_early_setup_x();
-
        if (needs_reset) {
                printk(BIOS_INFO, "ht reset -\n");
                soft_reset();
@@ -186,4 +158,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        post_cache_as_ram();
 }
-