##
## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
+## (coreboot plus bootloader) will live in the boot rom chip.
##
if USE_FALLBACK_IMAGE
default ROM_SECTION_SIZE = FALLBACK_SIZE
##
## Compute the start location and size size of
-## The linuxBIOS bootloader.
+## The coreboot bootloader.
##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default CONFIG_ROM_STREAM = 1
+default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default CONFIG_ROM_PAYLOAD = 1
##
-## Compute where this copy of linuxBIOS will start in the boot rom
+## Compute where this copy of coreboot will start in the boot rom
##
-default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
+## Compute a range of ROM that can cached to speed up coreboot,
## execution speed.
##
## XIP_ROM_SIZE must be a power of 2.
default XIP_ROM_SIZE=65536
default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-arch i386 end
+arch i386 end
##
driver mainboard.o
#dir /drivers/ati/ragexl
+
#needed by irq_tables and mptable and acpi_tables
object get_bus_conf.o
-
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o
+if HAVE_ACPI_TABLES
+ object acpi_tables.o
+ makerule dsdt.c
+ depends "$(MAINBOARD)/dsdt.dsl"
+ action "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.dsl"
+ action "mv dsdt.hex dsdt.c"
+ end
+ object ./dsdt.o
+ #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
+ #./fadt.o is moved to southbridge/nvidia/ck804/Config.lb
+end
+
if USE_DCACHE_RAM
if CONFIG_USE_INIT
-
-makerule ./auto.o
- depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
- action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
-end
-
+ makerule ./auto.o
+ depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
+ end
else
-
-makerule ./auto.inc
- depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
- action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
- action "perl -e 's/.rodata/.rom.data/g' -pi $@"
- action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+ makerule ./auto.inc
+ depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@"
+ action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
+ action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
+ end
end
-end
else
+ ##
+ ## Romcc output
+ ##
+ makerule ./failover.E
+ depends "$(MAINBOARD)/failover.c ../romcc"
+ action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+ end
-##
-## Romcc output
-##
-makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ./romcc"
- action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ./romcc"
- action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
+ makerule ./failover.inc
+ depends "$(MAINBOARD)/failover.c ../romcc"
+ action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+ end
-makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
- action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
- action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
+ makerule ./auto.E
+ depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+ action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+ end
+ makerule ./auto.inc
+ depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
+ action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+ end
end
##
-## Build our 16 bit and 32 bit linuxBIOS entry code
+## Build our 16 bit and 32 bit coreboot entry code
##
if USE_FALLBACK_IMAGE
- mainboardinit cpu/x86/16bit/entry16.inc
- ldscript /cpu/x86/16bit/entry16.lds
+ mainboardinit cpu/x86/16bit/entry16.inc
+ ldscript /cpu/x86/16bit/entry16.lds
end
mainboardinit cpu/x86/32bit/entry32.inc
end
if CONFIG_USE_INIT
- ldscript /cpu/amd/car/cache_as_ram.lds
+ ldscript /cpu/amd/car/cache_as_ram.lds
end
end
##
-## Build our reset vector (This is where linuxBIOS is entered)
+## Build our reset vector (This is where coreboot is entered)
##
-if USE_FALLBACK_IMAGE
- mainboardinit cpu/x86/16bit/reset16.inc
- ldscript /cpu/x86/16bit/reset16.lds
+if USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
else
- mainboardinit cpu/x86/32bit/reset32.inc
- ldscript /cpu/x86/32bit/reset32.lds
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
end
if USE_DCACHE_RAM
else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
+ ### Should this be in the northbridge code?
+ mainboardinit arch/i386/lib/cpu_reset.inc
end
##
end
if USE_DCACHE_RAM
-##
-## Setup Cache-As-Ram
-##
-mainboardinit cpu/amd/car/cache_as_ram.inc
+ ##
+ ## Setup Cache-As-Ram
+ ##
+ mainboardinit cpu/amd/car/cache_as_ram.inc
end
###
-### This is the early phase of linuxBIOS startup
+### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
- ldscript /arch/i386/lib/failover.lds
-else
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
-end
+ if USE_DCACHE_RAM
+ ldscript /arch/i386/lib/failover.lds
+ else
+ ldscript /arch/i386/lib/failover.lds
+ mainboardinit ./failover.inc
+ end
end
###
##
if USE_DCACHE_RAM
-if CONFIG_USE_INIT
-initobject auto.o
-else
-mainboardinit ./auto.inc
-end
+ if CONFIG_USE_INIT
+ initobject auto.o
+ else
+ mainboardinit ./auto.inc
+ end
else
-# ROMCC
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
+ # ROMCC
+ mainboardinit cpu/x86/fpu/enable_fpu.inc
+ mainboardinit cpu/x86/mmx/enable_mmx.inc
+ mainboardinit cpu/x86/sse/enable_sse.inc
+ mainboardinit ./auto.inc
+ mainboardinit cpu/x86/sse/disable_sse.inc
+ mainboardinit cpu/x86/mmx/disable_mmx.inc
end
##
-## Include the secondary Configuration files
+## Include the secondary Configuration files
##
-if CONFIG_CHIP_NAME
- config chip.h
-end
-
+config chip.h
# sample config for tyan/s2892
chip northbridge/amd/amdk8/root_complex
- device apic_cluster 0 on
- chip cpu/amd/socket_940
- device apic 0 on end
- end
- end
-
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ end
device pci_domain 0 on
chip northbridge/amd/amdk8 #mc0
- device pci 18.0 on # northbridge
- # devices on link 0, link 0 == LDT 0
- chip southbridge/nvidia/ck804
+ device pci 18.0 on # northbridge
+ # devices on link 0, link 0 == LDT 0
+ chip southbridge/nvidia/ck804
device pci 0.0 on end # HT
- device pci 1.0 on # LPC
- chip superio/winbond/w83627hf
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.6 off # CIR
- io 0x60 = 0x100
- end
- device pnp 2e.7 off # GAME_MIDI_GIPO1
- io 0x60 = 0x220
- io 0x62 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.8 off end # GPIO2
- device pnp 2e.9 off end # GPIO3
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- irq 0x70 = 5
- end
- end
+ device pci 1.0 on # LPC
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 3
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
end
- device pci 1.1 on # SM 0
- chip drivers/generic/generic #dimm 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic #dimm 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic #dimm 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic #dimm 0-1-1
- device i2c 53 on end
- end
- chip drivers/generic/generic #dimm 1-0-0
- device i2c 54 on end
- end
- chip drivers/generic/generic #dimm 1-0-1
- device i2c 55 on end
- end
- chip drivers/generic/generic #dimm 1-1-0
- device i2c 56 on end
- end
- chip drivers/generic/generic #dimm 1-1-1
- device i2c 57 on end
- end
- end # SM
- device pci 1.1 on # SM 1
+ device pci 1.1 on # SM 0
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-0
+ device i2c 54 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-1
+ device i2c 55 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-0
+ device i2c 56 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-1
+ device i2c 57 on end
+ end
+ end # SM
+ device pci 1.1 on # SM 1
chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4
- device i2c 2d on end
- end
- chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5
- device i2c 2e on end
- end
- chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN
- device i2c 2a on end
- end
- chip drivers/generic/generic # Winbond HWM 0x92
- device i2c 49 on end
- end
- chip drivers/generic/generic # Winbond HWM 0x94
- device i2c 4a on end
- end
+ device i2c 2d on end
+ end
+ chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5
+ device i2c 2e on end
+ end
+ chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN
+ device i2c 2a on end
+ end
+ chip drivers/generic/generic # Winbond HWM 0x92
+ device i2c 49 on end
+ end
+ chip drivers/generic/generic # Winbond HWM 0x94
+ device i2c 4a on end
+ end
end #SM
- device pci 2.0 on end # USB 1.1
- device pci 2.1 on end # USB 2
- device pci 4.0 off end # ACI
- device pci 4.1 off end # MCI
- device pci 6.0 on end # IDE
- device pci 7.0 on end # SATA 1
- device pci 8.0 on end # SATA 0
- device pci 9.0 on # PCI
+ device pci 2.0 on end # USB 1.1
+ device pci 2.1 on end # USB 2
+ device pci 4.0 off end # ACI
+ device pci 4.1 off end # MCI
+ device pci 6.0 on end # IDE
+ device pci 7.0 on end # SATA 1
+ device pci 8.0 on end # SATA 0
+ device pci 9.0 on # PCI
# chip drivers/ati/ragexl
chip drivers/pci/onboard
device pci 6.0 on end
register "rom_address" = "0xfff80000"
end
- chip drivers/pci/onboard
- device pci 8.0 on end
- end
+ chip drivers/pci/onboard
+ device pci 8.0 on end
+ end
end
- device pci a.0 off end # NIC
- device pci b.0 off end # PCI E 3
- device pci c.0 off end # PCI E 2
- device pci d.0 on end # PCI E 1
- device pci e.0 on end # PCI E 0
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
+ device pci a.0 off end # NIC
+ device pci b.0 off end # PCI E 3
+ device pci c.0 off end # PCI E 2
+ device pci d.0 on end # PCI E 1
+ device pci e.0 on end # PCI E 0
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ register "sata0_enable" = "1"
+ register "sata1_enable" = "1"
end
- end # device pci 18.0
+ end # device pci 18.0
device pci 18.0 on end # Link 1
device pci 18.0 on
- # devices on link 2, link 2 == LDT 2
- chip southbridge/amd/amd8131
- # the on/off keyword is mandatory
- device pci 0.0 on end
- device pci 0.1 on end
- device pci 1.0 on
- chip drivers/pci/onboard
- device pci 9.0 on end # broadcom 5704
+ # devices on link 2, link 2 == LDT 2
+ chip southbridge/amd/amd8131
+ # the on/off keyword is mandatory
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 1.0 on
+ chip drivers/pci/onboard
+ device pci 9.0 on end # broadcom 5704
device pci 9.1 on end
- end
+ end
end
- device pci 1.1 on end
- end
+ device pci 1.1 on end
+ end
end # device pci 18.0
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
end #mc0
-
+
end # pci_domain
-
-# chip drivers/generic/debug
-# device pnp 0.0 off end
-# device pnp 0.1 off end
-# device pnp 0.2 off end
-# device pnp 0.3 off end
-# device pnp 0.4 off end
+
+# chip drivers/generic/debug
+# device pnp 0.0 off end
+# device pnp 0.1 off end
+# device pnp 0.2 off end
+# device pnp 0.3 off end
+# device pnp 0.4 off end
# device pnp 0.5 on end
-# end
+# end
end # root_complex
projects / coreboot.git / blobdiff