Drop excessive whitespace randomly sprinkled in romstage.c files.

[coreboot.git] / src / mainboard / tyan / s2891 / romstage.c

diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c
index 0505493dc11f6d0c7eb6cec5598f837cd6631027..75405753e9bd21870faa1b980d2e1a6d21012a85 100644 (file)
--- a/src/mainboard/tyan/s2891/romstage.c
+++ b/src/mainboard/tyan/s2891/romstage.c
@@ -1,13 +1,3 @@
-#define ASSEMBLY 1
-#define __PRE_RAM__
-
-//used by raminit
-#define QRANK_DIMM_SUPPORT 1
-
-#if CONFIG_LOGICAL_CPUS==1
-#define SET_NB_CFG_54 1
-#endif
-
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -15,16 +5,13 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "lib/ramtest.c"
-
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <lib.h>
+#include <spd.h>
 #include <cpu/amd/model_fxx_rev.h>
-
 #include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "southbridge/nvidia/ck804/ck804_early_smbus.c"
+#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
@@ -32,10 +19,8 @@
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@@ -61,29 +46,16 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "lib/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "resourcemap.c"
-
+#include "resourcemap.c" /* tyan does not want the default */
 #include "cpu/amd/dualcore/dualcore.c"
-
-#define CK804_NUM 1
 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
-
-#include "cpu/amd/car/copy_and_run.c"
-
 #include "cpu/amd/car/post_cache_as_ram.c"
-
 #include "cpu/amd/model_fxx/init_cpus.c"
-
-#include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
 
 static void sio_setup(void)
 {
-
-       unsigned value;
        uint32_t dword;
        uint8_t byte;
 
@@ -105,19 +77,17 @@ static void sio_setup(void)
        dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
        dword |= (1<<16);
        pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
-
 #endif
-
 }
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
        static const uint16_t spd_addr [] = {
-               (0xa<<3)|0, (0xa<<3)|2, 0, 0,
-               (0xa<<3)|1, (0xa<<3)|3, 0, 0,
+               DIMM0, DIMM2, 0, 0,
+               DIMM1, DIMM3, 0, 0,
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
-               (0xa<<3)|4, (0xa<<3)|6, 0, 0,
-               (0xa<<3)|5, (0xa<<3)|7, 0, 0,
+               DIMM4, DIMM6, 0, 0,
+               DIMM5, DIMM7, 0, 0,
 #endif
        };
 
@@ -127,16 +97,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        struct mem_controller ctrl[8];
        unsigned nodes;
 
-       if (!((cpu_init_detectedx) || (!boot_cpu()))) {
+       if (!cpu_init_detectedx && boot_cpu()) {
                /* Nothing special needs to be done to find bus 0 */
                /* Allow the HT devices to be found */
 
                enumerate_ht_chain();
 
                sio_setup();
-
-               /* Setup the ck804 */
-               ck804_enable_rom();
        }
 
        if (bist == 0) {
@@ -172,7 +139,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        needs_reset |= ck804_early_setup_x();
 
        if (needs_reset) {
-               printk_info("ht reset -\r\n");
+               printk(BIOS_INFO, "ht reset -\n");
                soft_reset();
        }
 
@@ -203,3 +170,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        post_cache_as_ram();
 }
+