Thanks to Myles' patch adding support for include statements,

[coreboot.git] / src / mainboard / tyan / s2891 / Config.lb

diff --git a/src/mainboard/tyan/s2891/Config.lb b/src/mainboard/tyan/s2891/Config.lb
index e7a8ac3850963b6a0ede577534600e1963bf2ae5..944b95d1fe012217351772c53fdb3679e71fe3e6 100644 (file)
--- a/src/mainboard/tyan/s2891/Config.lb
+++ b/src/mainboard/tyan/s2891/Config.lb
@@ -1,41 +1,8 @@
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-       default ROM_SECTION_SIZE   = FALLBACK_SIZE
-       default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
-       default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
-       default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The coreboot bootloader.
-##
-default PAYLOAD_SIZE        = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+include /config/nofailovercalculation.lb
 default CONFIG_ROM_PAYLOAD       = 1
 
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-
 arch i386 end
 
-
 ##
 ## Build the objects we have code for in this directory.
 ##
@@ -63,48 +30,20 @@ if HAVE_ACPI_TABLES
        #./fadt.o is moved to southbridge/nvidia/ck804/Config.lb
 end
 
-if USE_DCACHE_RAM
-
 if CONFIG_USE_INIT
        makerule ./auto.o
                depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-               action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
+               action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
        end
 else
        makerule ./auto.inc
                depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
-               action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall $(DEBUG_CFLAGS) -c -S -o $@"
+               action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
                action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
                action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
        end
 end
 
-else
-       ##
-       ## Romcc output
-       ##
-       makerule ./failover.E
-               depends "$(MAINBOARD)/failover.c ../romcc"
-               action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-       end
-
-       makerule ./failover.inc
-               depends "$(MAINBOARD)/failover.c ../romcc"
-               action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-       end
-
-       makerule ./auto.E
-               depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-               action  "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-       end
-
-       makerule ./auto.inc
-               depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
-               action  "../romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-       end
-
-end
-
 ##
 ## Build our 16 bit and 32 bit coreboot entry code
 ##
@@ -115,7 +54,6 @@ end
 
 mainboardinit cpu/x86/32bit/entry32.inc
 
-if USE_DCACHE_RAM
        if CONFIG_USE_INIT
                ldscript /cpu/x86/32bit/entry32.lds
        end
@@ -123,7 +61,6 @@ if USE_DCACHE_RAM
        if CONFIG_USE_INIT
                ldscript /cpu/amd/car/cache_as_ram.lds
        end
-end
 
 ##
 ## Build our reset vector (This is where coreboot is entered)
@@ -136,12 +73,6 @@ else
        ldscript /cpu/x86/32bit/reset32.lds
 end
 
-if USE_DCACHE_RAM
-else
-       ### Should this be in the northbridge code?
-       mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
 ##
 ## Include an id string (For safe flashing)
 ##
@@ -156,12 +87,10 @@ if USE_FALLBACK_IMAGE
        ldscript /southbridge/nvidia/ck804/romstrap.lds
 end
 
-if USE_DCACHE_RAM
        ##
        ## Setup Cache-As-Ram
        ##
        mainboardinit cpu/amd/car/cache_as_ram.inc
-end
 
 ###
 ### This is the early phase of coreboot startup
@@ -170,10 +99,6 @@ end
 ###
 if USE_FALLBACK_IMAGE
        ldscript /arch/i386/lib/failover.lds
-       if USE_DCACHE_RAM
-       else
-               mainboardinit ./failover.inc
-       end
 end
 
 ###
@@ -183,25 +108,12 @@ end
 ##
 ## Setup RAM
 ##
-if USE_DCACHE_RAM
-
        if CONFIG_USE_INIT
                initobject auto.o
        else
                mainboardinit ./auto.inc
        end
 
-else
-       # ROMCC
-       mainboardinit cpu/x86/fpu/enable_fpu.inc
-       mainboardinit cpu/x86/mmx/enable_mmx.inc
-       mainboardinit cpu/x86/sse/enable_sse.inc
-       mainboardinit ./auto.inc
-       mainboardinit cpu/x86/sse/disable_sse.inc
-       mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
 ##
 ## Include the secondary Configuration files
 ##