Apply linuxbios-rename-other-payload-options.patch

[coreboot.git] / src / mainboard / tyan / s2885 / Config.lb

diff --git a/src/mainboard/tyan/s2885/Config.lb b/src/mainboard/tyan/s2885/Config.lb
index a974cb5644c7bec17e67c610b10a404b7e015fb2..795485df6dfc5837c698c9ccaec4052c4f14f910 100644 (file)
--- a/src/mainboard/tyan/s2885/Config.lb
+++ b/src/mainboard/tyan/s2885/Config.lb
@@ -15,12 +15,12 @@ end
 ## The linuxBIOS bootloader.
 ##
 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
 
 ##
 ## Compute where this copy of linuxBIOS will start in the boot rom
 ##
-default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
 
 ##
 ## Compute a range of ROM that can cached to speed up linuxBIOS,
@@ -40,9 +40,32 @@ arch i386 end
 
 driver mainboard.o
 
+#dir /drivers/si/3114
+object get_bus_conf.o
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
 
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+
+makerule ./auto.o
+        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" 
+end
+
+else    
+                
+makerule ./auto.inc
+        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+        action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"         
+        action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+        action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+end
+
+end
+else
+  
 ##
 ## Romcc output
 ##
@@ -65,13 +88,26 @@ makerule ./auto.inc
         action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 end
 
+end
 ##
 ## Build our 16 bit and 32 bit linuxBIOS entry code
 ##
-mainboardinit cpu/x86/16bit/entry16.inc
+if USE_FALLBACK_IMAGE
+        mainboardinit cpu/x86/16bit/entry16.inc
+        ldscript /cpu/x86/16bit/entry16.lds
+end
+
 mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
+
+if USE_DCACHE_RAM
+        if CONFIG_USE_INIT
+                ldscript /cpu/x86/32bit/entry32.lds
+        end
+
+        if CONFIG_USE_INIT
+                ldscript      /cpu/amd/car/cache_as_ram.lds
+        end
+end
 
 ##
 ## Build our reset vector (This is where linuxBIOS is entered)
@@ -84,8 +120,11 @@ else
        ldscript /cpu/x86/32bit/reset32.lds 
 end
 
+if USE_DCACHE_RAM
+else
 ### Should this be in the northbridge code?
 mainboardinit arch/i386/lib/cpu_reset.inc
+end
 
 ##
 ## Include an id string (For safe flashing)
@@ -93,20 +132,44 @@ mainboardinit arch/i386/lib/cpu_reset.inc
 mainboardinit arch/i386/lib/id.inc
 ldscript /arch/i386/lib/id.lds
 
+if USE_DCACHE_RAM
+##
+## Setup Cache-As-Ram
+##
+mainboardinit cpu/amd/car/cache_as_ram.inc
+end
+
 ###
 ### This is the early phase of linuxBIOS startup 
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
 if USE_FALLBACK_IMAGE
-       ldscript /arch/i386/lib/failover.lds 
-       mainboardinit ./failover.inc
+if USE_DCACHE_RAM
+       ldscript /arch/i386/lib/failover.lds
+else
+       ldscript /arch/i386/lib/failover.lds
+        mainboardinit ./failover.inc
+end
 end
 
 ###
 ### O.k. We aren't just an intermediary anymore!
 ###
 
+##
+## Setup RAM
+##
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+initobject auto.o
+else
+mainboardinit ./auto.inc
+end
+
+else
+
 ##
 ## Setup RAM
 ##
@@ -117,24 +180,22 @@ mainboardinit ./auto.inc
 mainboardinit cpu/x86/sse/disable_sse.inc
 mainboardinit cpu/x86/mmx/disable_mmx.inc
 
+end
+
 ##
 ## Include the secondary Configuration files 
 ##
-
 if CONFIG_CHIP_NAME
        config chip.h
 end
 
 # sample config for tyan/s2885
 chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on                
-                chip cpu/amd/socket_940                 
-                        device apic 0 on end    
-                end                             
-#               chip cpu/amd/socket_940                 
-#                       device apic 1 on end    
-#               end                             
-        end 
+        device apic_cluster 0 on
+                chip cpu/amd/socket_940
+                        device apic 0 on end
+                end
+        end
        device pci_domain 0 on
                chip northbridge/amd/amdk8
                        device pci 18.0 on # LDT0
@@ -149,7 +210,11 @@ chip northbridge/amd/amdk8/root_complex
                                #  devices on link 2, link 2 == LDT 2
                                chip southbridge/amd/amd8131
                                        # the on/off keyword is mandatory
-                                       device pci 0.0 on end
+                                       device pci 0.0 on 
+                                                chip drivers/pci/onboard
+                                                        device pci 9.0 on end # broadcom 5703
+                                                end
+                                       end
                                        device pci 0.1 on end
                                        device pci 1.0 on end
                                        device pci 1.1 on end
@@ -162,6 +227,9 @@ chip northbridge/amd/amdk8/root_complex
                                                device pci 0.1 on end
                                                device pci 0.2 off end
                                                device pci 1.0 off end
+                                                chip drivers/pci/onboard
+                                                        device pci b.0 on end # SiI 3114
+                                                end
                                        end
                                        device pci 1.0 on
                                                chip superio/winbond/w83627hf
@@ -195,7 +263,7 @@ chip northbridge/amd/amdk8/root_complex
                                                                io 0x60 = 0x220
                                                                io 0x62 = 0x300
                                                                irq 0x70 = 9
-                                                       end
+                                                       end                                             
                                                        device pnp 2e.8 off end #  GPIO2
                                                        device pnp 2e.9 off end #  GPIO3
                                                        device pnp 2e.a off end #  ACPI
@@ -245,21 +313,15 @@ chip northbridge/amd/amdk8/root_complex
                        device pci 18.3 on end
                end
 
-#              chip northbridge/amd/amdk8
-#                      device pci 19.0 on end
-#                      device pci 19.0 on end
-#                      device pci 19.0 on end
-#                      device pci 19.1 on end
-#                      device pci 19.2 on end
-#                      device pci 19.3 on end
-#              end
-       end 
+       end #pci_domain
 
 #        chip drivers/generic/debug 
-#                device pnp 0.0 on end
+#                device pnp 0.0 off end
 #                device pnp 0.1 off end 
 #                device pnp 0.2 off end
-#                device pnp 0.3 on end
+#                device pnp 0.3 off end
+#              device pnp 0.4 off end
+#              device pnp 0.5 on end
 #        end
 end