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[coreboot.git] / src / mainboard / tyan / s2880 / auto.c

diff --git a/src/mainboard/tyan/s2880/auto.c b/src/mainboard/tyan/s2880/auto.c
index 9b3252a890794ed8336fbebd00e24284cc4d78b1..6384f4d152423b0b6f90280659590a1e1c319757 100644 (file)
--- a/src/mainboard/tyan/s2880/auto.c
+++ b/src/mainboard/tyan/s2880/auto.c
@@ -5,7 +5,8 @@
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -14,13 +15,15 @@
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/k8/apic_timer.c"
+#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include "northbridge/amd/amdk8/cpu_rev.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -39,24 +42,30 @@ static void soft_reset(void)
         set_bios_reset();
         pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
 }
-#define REV_B_RESET 0
+static void soft2_reset(void)
+{  
+        set_bios_reset();
+        pci_write_config8(PCI_DEV(3, 0x04, 0), 0x47, 1);
+}
+
 static void memreset_setup(void)
 {
-#if REV_B_RESET==1
+   if (is_cpu_pre_c0()) {
         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=0
-#else
+   }
+   else {
         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-#endif
+   }
         outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); 
 }
 
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
+   if (is_cpu_pre_c0()) {
         udelay(800);
-#if REV_B_RESET==1
         outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
-#endif
         udelay(90);
+   }
 }
 
 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
@@ -84,7 +93,7 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
         */
 
        uint32_t ret=0x00010101; /* default row entry */
-
+       /* Link1 of CPU0 to Link1 of CPU1 */
        static const unsigned int rows_2p[2][2] = {
                { 0x00050101, 0x00010404 },
                { 0x00010404, 0x00050101 }
@@ -113,17 +122,18 @@ static inline int spd_read_byte(unsigned device, unsigned address)
        return smbus_read_byte(device, address);
 }
 
-/* include mainboard specific ht code */
-#include "hypertransport.c"
 
+//#include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "northbridge/amd/amdk8/raminit.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
 #include "sdram/generic_sdram.c"
 
+#include "northbridge/amd/amdk8/resourcemap.c" 
+
 #define FIRST_CPU  1
 #define SECOND_CPU 1
 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(void)
+static void main(unsigned long bist)
 {
        static const struct mem_controller cpu[] = {
 #if FIRST_CPU
@@ -150,23 +160,37 @@ static void main(void)
 #endif
        };
         int needs_reset;
-        enable_lapic();
-        init_timer();
-        if (cpu_init_detected()) {
-                asm("jmp __cpu_reset");
-        }
-        distinguish_cpu_resets();
-        if (!boot_cpu()) {
-                stop_this_cpu();
-        }
+       unsigned nodeid;
+
+        if (bist == 0) {
+                /* Skip this if there was a built in self test failure */
+                amd_early_mtrr_init();
+                enable_lapic();
+                init_timer();
+               
+               nodeid = lapicid() & 0xf;
+
+                if (cpu_init_detected(nodeid)) {
+                        asm volatile ("jmp __cpu_reset");
+                }
+                distinguish_cpu_resets(nodeid);
+                if (!boot_cpu()) {
+                        stop_this_cpu();
+                }       
+        }               
+                        
         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
-        uart_init();
-        console_init();
+        uart_init();    
+        console_init(); 
+                
+        /* Halt if there was a built in self test failure */
+//      report_bist_failure(bist);
+
         setup_default_resource_map();
         needs_reset = setup_coherent_ht_domain();
         needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
         if (needs_reset) {
-                print_info("ht reset -");
+                print_info("ht reset -\r\n");
                 soft_reset();
         }