-
+
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/setup_resource_map.c"
#endif
#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/copy_and_run.c"
+
#include "cpu/amd/car/post_cache_as_ram.c"
}
// post_code(0x32);
-
+
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
setup_default_resource_map();
needs_reset = setup_coherent_ht_domain();
-
+
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
start_other_cores();