#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
#include <cpu/amd/lxdef.h>
-#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
-#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
-#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
static inline int spd_read_byte(unsigned int device, unsigned int address)
{
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
#include "lib/generic_sdram.c"
-#include "cpu/amd/model_lx/cpureginit.c"
-#include "cpu/amd/model_lx/syspreinit.c"
-#include "cpu/amd/model_lx/msrinit.c"
+#include "cpu/amd/geode_lx/cpureginit.c"
+#include "cpu/amd/geode_lx/syspreinit.c"
+#include "cpu/amd/geode_lx/msrinit.c"
void main(unsigned long bist)
{
- post_code(0x01);
-
static const struct mem_controller memctrl[] = {
{.channel0 = {DIMM0, DIMM1}}
};
*/
/* If debug. real setup done in chipset init via devicetree.cb. */
cs5536_setup_onchipuart(1);
- uart_init();
console_init();
/* Halt if there was a built in self test failure */
sdram_initialize(1, memctrl);
- /* Check memory. */
- /* ram_check(0x00000000, 640 * 1024); */
-
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}