#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <arch/llshell.h>
-#include "pc80/serial.c"
#include "pc80/udelay_io.c"
-#include "arch/i386/lib/console.c"
-#include "lib/ramtest.c"
+#include <console/console.h>
+#include <lib.h>
#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
#include "northbridge/intel/i82830/raminit.h"
#include "northbridge/intel/i82830/memory_initialized.c"
#include "southbridge/intel/i82801dx/i82801dx.h"
#include "southbridge/intel/i82801dx/i82801dx_reset.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "spd_table.h"
#include "gpio.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
-
#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
#include "southbridge/intel/i82801dx/i82801dx_tco_timer.c"
+#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
+
/**
* The onboard 64MB PC133 memory does not have a SPD EEPROM so the
* values have to be set manually, the SO-DIMM socket is located in
- * socket0 (0x50), and the onboard memory is located in socket1 (0x51).
+ * socket0 (0x50/DIMM0), and the onboard memory is located in socket1
+ * (0x51/DIMM1).
*/
static inline int spd_read_byte(unsigned device, unsigned address)
{
int i;
- if (device == 0x50) {
+ if (device == DIMM0) {
return smbus_read_byte(device, address);
- } else if (device == 0x51) {
+ } else if (device == DIMM1) {
for (i = 0; i < ARRAY_SIZE(spd_table); i++) {
if (spd_table[i].address == address)
return spd_table[i].data;
/* CPU Frequency Strap */
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd5, 0x02);
/* ACPI base address and enable Resource Indicator */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1));
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1));
/* Enable the SMBUS */
enable_smbus();
/* ACPI Enable */
pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10);
}
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
if (bist == 0) {
- early_mtrr_init();
- if (memory_initialized()) {
+ if (memory_initialized())
hard_reset();
- }
}
/* Set southbridge and superio gpios */
/* ram_check(0, 640 * 1024); */
/* ram_check(64512 * 1024, 65536 * 1024); */
}
-