#include <device/device.h>
#include <device/pci.h>
#include <arch/io.h>
-#include <boot/coreboot_tables.h>
+#include <boot/tables.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
-#include <../southbridge/amd/sb600/sb600.h>
+#include <southbridge/amd/sb600/sb600.h>
#include "chip.h"
#define ADT7461_ADDRESS 0x4C
extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
u8 val);
-extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
- uint64_t start, uint64_t size);
#define ADT7461_read_byte(address) \
do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
#define ARA_read_byte(address) \
/***************************************************
* This board, the TIM-8690 has two Marvel 88e5056 PCI-E
-* 10/100/1000 chips on board.
+* 10/100/1000 chips on board.
* Both of their pin PERSTn pins are connected to GPIO 5 of the
* SB600 southbridge.
****************************************************/
* enable the dedicated function in tim8690 board.
* This function called early than rs690_enable.
*************************************************/
-void tim8690_enable(device_t dev)
+static void tim8690_enable(device_t dev)
{
- struct mainboard_config *mainboard =
- (struct mainboard_config *)dev->chip_info;
-
printk(BIOS_INFO, "Mainboard tim8690 Enable. dev=0x%p\n", dev);
#if (CONFIG_GFXUMA == 1)
lb_add_memory_range(mem, LB_MEM_RESERVED,
uma_memory_base, uma_memory_size);
#endif
+ return 0;
}
struct chip_operations mainboard_ops = {